Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 (72f35423) · Commits · 戴 / test

Documentation/ABI/testing/sysfs-driver-uacce

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		What: /sys/class/uacce/<dev_name>/api
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Api of the device
		Can be any string and up to userspace to parse.
		Application use the api to match the correct driver

		What: /sys/class/uacce/<dev_name>/flags
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Attributes of the device, see UACCE_DEV_xxx flag defined in uacce.h

		What: /sys/class/uacce/<dev_name>/available_instances
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Available instances left of the device
		Return -ENODEV if uacce_ops get_available_instances is not provided

		What: /sys/class/uacce/<dev_name>/algorithms
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Algorithms supported by this accelerator, separated by new line.
		Can be any string and up to userspace to parse.

		What: /sys/class/uacce/<dev_name>/region_mmio_size
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Size (bytes) of mmio region queue file

		What: /sys/class/uacce/<dev_name>/region_dus_size
		Date: Feb 2020
		KernelVersion: 5.7
		Contact: linux-accelerators@lists.ozlabs.org
		Description: Size (bytes) of dus region queue file

Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings

		maintainers:
		- Kalyani Akula <kalyani.akula@xilinx.com>
		- Michal Simek <michal.simek@xilinx.com>

		description: \|
		The ZynqMP AES-GCM hardened cryptographic accelerator is used to
		encrypt or decrypt the data with provided key and initialization vector.

		properties:
		compatible:
		const: xlnx,zynqmp-aes

		required:
		- compatible

		additionalProperties: false

		examples:
		- \|
		firmware {
		zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";
		xlnx_aes: zynqmp-aes {
		compatible = "xlnx,zynqmp-aes";
		};
		};
		};
		...

Documentation/misc-devices/uacce.rst

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		.. SPDX-License-Identifier: GPL-2.0

		Introduction of Uacce
		---------------------

		Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
		provide Shared Virtual Addressing (SVA) between accelerators and processes.
		So accelerator can access any data structure of the main cpu.
		This differs from the data sharing between cpu and io device, which share
		only data content rather than address.
		Because of the unified address, hardware and user space of process can
		share the same virtual address in the communication.
		Uacce takes the hardware accelerator as a heterogeneous processor, while
		IOMMU share the same CPU page tables and as a result the same translation
		from va to pa.

		::

		__________________________ __________________________
		\| \| \| \|
		\| User application (CPU) \| \| Hardware Accelerator \|
		\|__________________________\| \|__________________________\|

		\| \|
		\| va \| va
		V V
		__________ __________
		\| \| \| \|
		\| MMU \| \| IOMMU \|
		\|__________\| \|__________\|
		\| \|
		\| \|
		V pa V pa
		_______________________________________
		\| \|
		\| Memory \|
		\|_______________________________________\|



		Architecture
		------------

		Uacce is the kernel module, taking charge of iommu and address sharing.
		The user drivers and libraries are called WarpDrive.

		The uacce device, built around the IOMMU SVA API, can access multiple
		address spaces, including the one without PASID.

		A virtual concept, queue, is used for the communication. It provides a
		FIFO-like interface. And it maintains a unified address space between the
		application and all involved hardware.

		::

		___________________ ________________
		\| \| user API \| \|
		\| WarpDrive library \| ------------> \| user driver \|
		\|___________________\| \|________________\|
		\| \|
		\| \|
		\| queue fd \|
		\| \|
		\| \|
		v \|
		___________________ _________ \|
		\| \| \| \| \| mmap memory
		\| Other framework \| \| uacce \| \| r/w interface
		\| crypto/nic/others \| \|_________\| \|
		\|___________________\| \|
		\| \| \|
		\| register \| register \|
		\| \| \|
		\| \| \|
		\| _________________ __________ \|
		\| \| \| \| \| \|
		------------- \| Device Driver \| \| IOMMU \| \|
		\|_________________\| \|__________\| \|
		\| \|
		\| V
		\| ___________________
		\| \| \|
		-------------------------- \| Device(Hardware) \|
		\|___________________\|


		How does it work
		----------------

		Uacce uses mmap and IOMMU to play the trick.

		Uacce creates a chrdev for every device registered to it. New queue is
		created when user application open the chrdev. The file descriptor is used
		as the user handle of the queue.
		The accelerator device present itself as an Uacce object, which exports as
		a chrdev to the user space. The user application communicates with the
		hardware by ioctl (as control path) or share memory (as data path).

		The control path to the hardware is via file operation, while data path is
		via mmap space of the queue fd.

		The queue file address space:

		::

		/**
		* enum uacce_qfrt: qfrt type
		* @UACCE_QFRT_MMIO: device mmio region
		* @UACCE_QFRT_DUS: device user share region
		*/
		enum uacce_qfrt {
		UACCE_QFRT_MMIO = 0,
		UACCE_QFRT_DUS = 1,
		};

		All regions are optional and differ from device type to type.
		Each region can be mmapped only once, otherwise -EEXIST returns.

		The device mmio region is mapped to the hardware mmio space. It is generally
		used for doorbell or other notification to the hardware. It is not fast enough
		as data channel.

		The device user share region is used for share data buffer between user process
		and device.


		The Uacce register API
		----------------------

		The register API is defined in uacce.h.

		::

		struct uacce_interface {
		char name[UACCE_MAX_NAME_SIZE];
		unsigned int flags;
		const struct uacce_ops *ops;
		};

		According to the IOMMU capability, uacce_interface flags can be:

		::

		/**
		* UACCE Device flags:
		* UACCE_DEV_SVA: Shared Virtual Addresses
		* Support PASID
		* Support device page faults (PCI PRI or SMMU Stall)
		*/
		#define UACCE_DEV_SVA BIT(0)

		struct uacce_device uacce_alloc(struct device parent,
		struct uacce_interface *interface);
		int uacce_register(struct uacce_device *uacce);
		void uacce_remove(struct uacce_device *uacce);

		uacce_register results can be:

		a. If uacce module is not compiled, ERR_PTR(-ENODEV)

		b. Succeed with the desired flags

		c. Succeed with the negotiated flags, for example

		uacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA

		So user driver need check return value as well as the negotiated uacce->flags.


		The user driver
		---------------

		The queue file mmap space will need a user driver to wrap the communication
		protocol. Uacce provides some attributes in sysfs for the user driver to
		match the right accelerator accordingly.
		More details in Documentation/ABI/testing/sysfs-driver-uacce.

MAINTAINERS

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		@@ -4577,7 +4577,9 @@ S: Supported
		F: drivers/scsi/cxgbi/cxgb3i

		CXGB4 CRYPTO DRIVER (chcr)
		M: Atul Gupta <atul.gupta@chelsio.com>
		M: Ayush Sawal <ayush.sawal@chelsio.com>
		M: Vinay Kumar Yadav <vinay.yadav@chelsio.com>
		M: Rohit Maheshwari <rohitm@chelsio.com>
		L: linux-crypto@vger.kernel.org
		W: http://www.chelsio.com
		S: Supported
		@@ -10066,6 +10068,7 @@ F: Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
		MARVELL CRYPTO DRIVER
		M: Boris Brezillon <bbrezillon@kernel.org>
		M: Arnaud Ebalard <arno@natisbad.org>
		M: Srujana Challa <schalla@marvell.com>
		F: drivers/crypto/marvell/
		S: Maintained
		L: linux-crypto@vger.kernel.org
		@@ -17139,6 +17142,18 @@ W: http://linuxtv.org
		S: Maintained
		F: drivers/media/pci/tw686x/

		UACCE ACCELERATOR FRAMEWORK
		M: Zhangfei Gao <zhangfei.gao@linaro.org>
		M: Zhou Wang <wangzhou1@hisilicon.com>
		L: linux-accelerators@lists.ozlabs.org
		L: linux-kernel@vger.kernel.org
		S: Maintained
		F: Documentation/ABI/testing/sysfs-driver-uacce
		F: Documentation/misc-devices/uacce.rst
		F: drivers/misc/uacce/
		F: include/linux/uacce.h
		F: include/uapi/misc/uacce/

		UBI FILE SYSTEM (UBIFS)
		M: Richard Weinberger <richard@nod.at>
		L: linux-mtd@lists.infradead.org

arch/arm/crypto/.gitignore

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Original line number	Diff line number	Diff line
		aesbs-core.S
		sha256-core.S
		sha512-core.S
		poly1305-core.S

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