Commit 72c0098d authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Linus Torvalds
Browse files

x86/mm: Reinitialize TLB state on hotplug and resume 



When Linux brings a CPU down and back up, it switches to init_mm and then
loads swapper_pg_dir into CR3.  With PCID enabled, this has the side effect
of masking off the ASID bits in CR3.

This can result in some confusion in the TLB handling code.  If we
bring a CPU down and back up with any ASID other than 0, we end up
with the wrong ASID active on the CPU after resume.  This could
cause our internal state to become corrupt, although major
corruption is unlikely because init_mm doesn't have any user pages.
More obviously, if CONFIG_DEBUG_VM=y, we'll trip over an assertion
in the next context switch.  The result of *that* is a failure to
resume from suspend with probability 1 - 1/6^(cpus-1).

Fix it by reinitializing cpu_tlbstate on resume and CPU bringup.

Reported-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
Reported-by: default avatarJiri Kosina <jikos@kernel.org>
Fixes: 10af6235 ("x86/mm: Implement PCID based optimization: try to preserve old TLB entries using PCID")
Signed-off-by: default avatarAndy Lutomirski <luto@kernel.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 80cee03b

arch/x86/include/asm/tlbflush.h

+2 −0
Original line number Diff line number Diff line
@@ -198,6 +198,8 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask) 
	cr4_set_bits(mask);

}



extern void initialize_tlbstate_and_flush(void);



static inline void __native_flush_tlb(void)

{

	/*

arch/x86/kernel/cpu/common.c

+2 −0
Original line number Diff line number Diff line
@@ -1583,6 +1583,7 @@ void cpu_init(void) 
	mmgrab(&init_mm);

	me->active_mm = &init_mm;

	BUG_ON(me->mm);

	initialize_tlbstate_and_flush();

	enter_lazy_tlb(&init_mm, me);



	load_sp0(t, &current->thread);
@@ -1637,6 +1638,7 @@ void cpu_init(void) 
	mmgrab(&init_mm);

	curr->active_mm = &init_mm;

	BUG_ON(curr->mm);

	initialize_tlbstate_and_flush();

	enter_lazy_tlb(&init_mm, curr);



	load_sp0(t, thread);

arch/x86/mm/tlb.c

+44 −0
Original line number Diff line number Diff line
@@ -213,6 +213,50 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 
	switch_ldt(real_prev, next);

}



/*

 * Call this when reinitializing a CPU.  It fixes the following potential

 * problems:

 *

 * - The ASID changed from what cpu_tlbstate thinks it is (most likely

 *   because the CPU was taken down and came back up with CR3's PCID

 *   bits clear.  CPU hotplug can do this.

 *

 * - The TLB contains junk in slots corresponding to inactive ASIDs.

 *

 * - The CPU went so far out to lunch that it may have missed a TLB

 *   flush.

 */

void initialize_tlbstate_and_flush(void)

{

	int i;

	struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);

	u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);

	unsigned long cr3 = __read_cr3();



	/* Assert that CR3 already references the right mm. */

	WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));



	/*

	 * Assert that CR4.PCIDE is set if needed.  (CR4.PCIDE initialization

	 * doesn't work like other CR4 bits because it can only be set from

	 * long mode.)

	 */

	WARN_ON(boot_cpu_has(X86_CR4_PCIDE) &&

		!(cr4_read_shadow() & X86_CR4_PCIDE));



	/* Force ASID 0 and force a TLB flush. */

	write_cr3(cr3 & ~CR3_PCID_MASK);



	/* Reinitialize tlbstate. */

	this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);

	this_cpu_write(cpu_tlbstate.next_asid, 1);

	this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);

	this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);



	for (i = 1; i < TLB_NR_DYN_ASIDS; i++)

		this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);

}



/*

 * flush_tlb_func_common()'s memory ordering requirement is that any

 * TLB fills that happen after we flush the TLB are ordered after we

arch/x86/power/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -181,6 +181,7 @@ static void fix_processor_context(void) 
#endif

	load_TR_desc();				/* This does ltr */

	load_mm_ldt(current->active_mm);	/* This does lldt */

	initialize_tlbstate_and_flush();



	fpu__resume_cpu();

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