Commit 72a7a992 authored May 06, 2020 by Zhenyu Wang

drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest



As i915 won't allocate extra PDP for current default PML4 table,
so for 3-level ppgtt guest, we would hit kernel pointer access
failure on extra PDP pointers. So this trys to bypass that now.
It won't impact real shadow PPGTT setup, so guest context still
works.

This is verified on 4.15 guest kernel with i915.enable_ppgtt=1
to force on old aliasing ppgtt behavior.

Fixes: 4f15665c ("drm/i915: Add ppgtt to GVT GEM context")
Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200506095918.124913-1-zhenyuw@linux.intel.com

parent f965b681

drivers/gpu/drm/i915/gvt/scheduler.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -379,7 +379,11 @@ static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
		for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
		struct i915_page_directory * const pd =
		i915_pd_entry(ppgtt->pd, i);

		/* skip now as current i915 ppgtt alloc won't allocate
		top level pdp for non 4-level table, won't impact
		shadow ppgtt. */
		if (!pd)
		break;
		px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
		}
		}

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