Commit 72a20cee authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "Here are some arm64 fixes for -rc5.

  The only non-trivial change (in terms of the diffstat) is fixing our
  SVE ptrace API for big-endian machines, but the majority of this is
  actually the addition of much-needed comments and updates to the
  documentation to try to avoid this mess biting us again in future.

  There are still a couple of small things on the horizon, but nothing
  major at this point.

  Summary:

   - Fix broken SVE ptrace API when running in a big-endian configuration

   - Fix performance regression due to off-by-one in TLBI range checking

   - Fix build regression when using Clang"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/sve: Fix missing SVE/FPSIMD endianness conversions
  arm64: tlbflush: Ensure start/end of address range are aligned to stride
  arm64: Don't unconditionally add -Wno-psabi to KBUILD_CFLAGS
parents fd6b99fa 41040cf7

Documentation/arm64/sve.txt

+16 −0
Original line number Diff line number Diff line
@@ -56,6 +56,18 @@ model features for SVE is included in Appendix A. 
  is to connect to a target process first and then attempt a

  ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).



* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory

  between userspace and the kernel, the register value is encoded in memory in

  an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at

  byte offset i from the start of the memory representation.  This affects for

  example the signal frame (struct sve_context) and ptrace interface

  (struct user_sve_header) and associated data.



  Beware that on big-endian systems this results in a different byte order than

  for the FPSIMD V-registers, which are stored as single host-endian 128-bit

  values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at

  byte offset i.  (struct fpsimd_context, struct user_fpsimd_state).





2.  Vector length terminology

-----------------------------
@@ -124,6 +136,10 @@ the SVE instruction set architecture. 
  size and layout.  Macros SVE_SIG_* are defined [1] to facilitate access to

  the members.



* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant

  layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the

  start of the register's representation in memory.



* If the SVE context is too big to fit in sigcontext.__reserved[], then extra

  space is allocated on the stack, an extra_context record is written in

  __reserved[] referencing this space.  sve_context is then written in the

arch/arm64/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ endif 


KBUILD_CFLAGS	+= -mgeneral-regs-only $(lseinstr) $(brokengasinst)

KBUILD_CFLAGS	+= -fno-asynchronous-unwind-tables

KBUILD_CFLAGS	+= -Wno-psabi

KBUILD_CFLAGS	+= $(call cc-disable-warning, psabi)

KBUILD_AFLAGS	+= $(lseinstr) $(brokengasinst)



KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)

arch/arm64/include/asm/tlbflush.h

+3 −0
Original line number Diff line number Diff line
@@ -195,6 +195,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, 
	unsigned long asid = ASID(vma->vm_mm);

	unsigned long addr;



	start = round_down(start, stride);

	end = round_up(end, stride);



	if ((end - start) >= (MAX_TLBI_OPS * stride)) {

		flush_tlb_mm(vma->vm_mm);

		return;

arch/arm64/include/uapi/asm/kvm.h

+7 −0
Original line number Diff line number Diff line
@@ -260,6 +260,13 @@ struct kvm_vcpu_events { 
	 KVM_REG_SIZE_U256 |						\

	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))



/*

 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and

 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-

 * invariant layout which differs from the layout used for the FPSIMD

 * V-registers on big-endian systems: see sigcontext.h for more explanation.

 */



#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN

#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX

arch/arm64/include/uapi/asm/ptrace.h

+4 −0
Original line number Diff line number Diff line
@@ -176,6 +176,10 @@ struct user_sve_header { 
 *	FPCR	uint32_t			FPCR

 *

 * Additional data might be appended in the future.

 *

 * The Z-, P- and FFR registers are represented in memory in an endianness-

 * invariant layout which differs from the layout used for the FPSIMD

 * V-registers on big-endian systems: see sigcontext.h for more explanation.

 */



#define SVE_PT_SVE_ZREG_SIZE(vq)	__SVE_ZREG_SIZE(vq)

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