Commit 7284635d authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k_hw: add support for the AR9003 2.2 



The checksums of the initvals are:

initvals -f ar9003-2p2
0x00000000c2bfa7d5        ar9300_2p2_radio_postamble
0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p2
0x00000000056eaf74        ar9300_2p2_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p2
0x0000000078658fb5        ar9300_2p2_mac_postamble
0x0000000023235333        ar9300_2p2_soc_postamble
0x0000000054d41904        ar9200_merlin_2p2_radio_core
0x000000008475a084        ar9300_2p2_baseband_postamble
0x000000009aaafd90        ar9300_2p2_baseband_core
0x000000003df9a326        ar9300Modes_high_power_tx_gain_table_2p2
0x000000001cfba124        ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000011302700        ar9300Common_rx_gain_table_2p2
0x00000000a9a2b114        ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000a9d66d40        ar9300_2p2_mac_core
0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a0c531c8        ar9300_2p2_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p2
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p2

Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 53b1b3e1

drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h

0 → 100644
+1785 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+136 −25
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "hw.h"

#include "ar9003_mac.h"

#include "ar9003_initvals.h"

#include "ar9003_2p2_initvals.h"



/* General hardware code for the AR9003 hadware family */
@@ -31,12 +32,8 @@ static bool ar9003_hw_macversion_supported(u32 macversion) 
	return false;

}



/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */

/*

 * XXX: move TX/RX gain INI to its own init_mode_gain_regs after

 * ensuring it does not affect hardware bring up

 */

static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

/* AR9003 2.0 */

static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)

{

	/* mac */

	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -106,27 +103,128 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
		       3);

}



/* AR9003 2.2 */

static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)

{

	/* mac */

	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);

	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

		       ar9300_2p2_mac_core,

		       ARRAY_SIZE(ar9300_2p2_mac_core), 2);

	INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],

		       ar9300_2p2_mac_postamble,

		       ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);



	/* bb */

	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);

	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],

		       ar9300_2p2_baseband_core,

		       ARRAY_SIZE(ar9300_2p2_baseband_core), 2);

	INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],

		       ar9300_2p2_baseband_postamble,

		       ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);



	/* radio */

	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);

	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],

		       ar9300_2p2_radio_core,

		       ARRAY_SIZE(ar9300_2p2_radio_core), 2);

	INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],

		       ar9300_2p2_radio_postamble,

		       ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);



	/* soc */

	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],

		       ar9300_2p2_soc_preamble,

		       ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);

	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);

	INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],

		       ar9300_2p2_soc_postamble,

		       ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);



	/* rx/tx gain */

	INIT_INI_ARRAY(&ah->iniModesRxGain,

		       ar9300Common_rx_gain_table_2p2,

		       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);

	INIT_INI_ARRAY(&ah->iniModesTxGain,

		       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,

		       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),

		       5);



	/* Load PCIE SERDES settings from INI */



	/* Awake Setting */



	INIT_INI_ARRAY(&ah->iniPcieSerdes,

		       ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,

		       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),

		       2);



	/* Sleep Setting */



	INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,

		       ar9300PciePhy_clkreq_enable_L1_2p2,

		       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),

		       2);



	/* Fast clock modal settings */

	INIT_INI_ARRAY(&ah->iniModesAdditional,

		       ar9300Modes_fast_clock_2p2,

		       ARRAY_SIZE(ar9300Modes_fast_clock_2p2),

		       3);

}



/*

 * The AR9003 family uses a new INI format (pre, core, post

 * arrays per subsystem).

 */

static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

{

	if (AR_SREV_9300_20(ah))

		ar9003_2p0_hw_init_mode_regs(ah);

	else

		ar9003_2p2_hw_init_mode_regs(ah);

}



static void ar9003_tx_gain_table_apply(struct ath_hw *ah)

{

	switch (ar9003_hw_get_tx_gain_idx(ah)) {

	case 0:

	default:

		if (AR_SREV_9300_20(ah))

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_lowest_ob_db_tx_gain_table_2p0,

				       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),

				       5);

		else

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,

				       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),

				       5);

		break;

	case 1:

		if (AR_SREV_9300_20(ah))

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_high_ob_db_tx_gain_table_2p0,

				       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),

				       5);

		else

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_high_ob_db_tx_gain_table_2p2,

				       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),

				       5);

		break;

	case 2:

		if (AR_SREV_9300_20(ah))

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_low_ob_db_tx_gain_table_2p0,

				       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),

				       5);

		else

			INIT_INI_ARRAY(&ah->iniModesTxGain,

				       ar9300Modes_low_ob_db_tx_gain_table_2p2,

				       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),

				       5);

		break;

	}

}
@@ -136,15 +234,28 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 
	switch (ar9003_hw_get_rx_gain_idx(ah)) {

	case 0:

	default:

		INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,

		if (AR_SREV_9300_20(ah))

			INIT_INI_ARRAY(&ah->iniModesRxGain,

				       ar9300Common_rx_gain_table_2p0,

				       ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),

				       2);

		else

			INIT_INI_ARRAY(&ah->iniModesRxGain,

				       ar9300Common_rx_gain_table_2p2,

				       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),

				       2);

		break;

	case 1:

		if (AR_SREV_9300_20(ah))

			INIT_INI_ARRAY(&ah->iniModesRxGain,

				       ar9300Common_wo_xlna_rx_gain_table_2p0,

				       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),

				       2);

		else

			INIT_INI_ARRAY(&ah->iniModesRxGain,

				       ar9300Common_wo_xlna_rx_gain_table_2p2,

				       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),

				       2);

		break;

	}

}

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