Commit 7253b85c authored by Simon Horman's avatar Simon Horman Committed by Russell King
Browse files

ARM: 7541/1: Add ARM ERRATA 775420 workaround 



arm: Add ARM ERRATA 775420 workaround

Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.

Based on work by Kouei Abe and feedback from Catalin Marinas.

Signed-off-by: default avatarKouei Abe <kouei.abe.cp@rms.renesas.com>
[ horms@verge.net.au: Changed to implementation
  suggested by catalin.marinas@arm.com ]
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarSimon Horman <horms@verge.net.au>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 63994137

arch/arm/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419 
	  on systems with an outer cache, the store buffer is drained

	  explicitly.



config ARM_ERRATA_775420

       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"

       depends on CPU_V7

       help

	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,

	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance

	 operation aborts with MMU exception, it might cause the processor

	 to deadlock. This workaround puts DSB before executing ISB if

	 an abort may occur on cache maintenance.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/mm/cache-v7.S

+3 −0
Original line number Diff line number Diff line
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range) 
 * isn't mapped, fail with -EFAULT.

 */

9001:

#ifdef CONFIG_ARM_ERRATA_775420

	dsb

#endif

	mov	r0, #-EFAULT

	mov	pc, lr

 UNWIND(.fnend		)

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