Commit 722ca51d authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: Remove redundant code in gfx_v8_0.c 



the CG related registers have been programed in golden setting
PG register default value is 0.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarHang Zhou <hang.zhou@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d944aaa

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+0 −20
Original line number Diff line number Diff line
@@ -4208,31 +4208,11 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) 
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)

{

	int r;

	u32 tmp;



	gfx_v8_0_rlc_stop(adev);



	/* disable CG */

	tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);

	tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |

		 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);

	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);

	if (adev->asic_type == CHIP_POLARIS11 ||

	    adev->asic_type == CHIP_POLARIS10 ||

	    adev->asic_type == CHIP_POLARIS12 ||

	    adev->asic_type == CHIP_VEGAM) {

		tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);

		tmp &= ~0x3;

		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);

	}



	/* disable PG */

	WREG32(mmRLC_PG_CNTL, 0);



	gfx_v8_0_rlc_reset(adev);

	gfx_v8_0_init_pg(adev);





	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {

		/* legacy rlc firmware loading */

		r = gfx_v8_0_rlc_load_microcode(adev);

CRA Git | Maintained and supported by SUSTech CRA and CCSE