Commit 72296bde authored by Paul Walmsley's avatar Paul Walmsley
Browse files

riscv: dts: add initial support for the SiFive FU540-C000 SoC 



Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.

This file is expected to grow as more device drivers are added to the
kernel.

This patch includes a fix to the QSPI memory map due to a
documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
entries for the I2C controller, and merges all DT changes that
formerly were made dynamically by the riscv-pk BBL proxy kernel.

Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Tested-by: default avatarLoys Ollivier <lollivier@baylibre.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: ShihPo Hung <shihpo.hung@sifive.com>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
parent 4fd669a8

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

0 → 100644
+215 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2018-2019 SiFive, Inc */



/dts-v1/;



#include <dt-bindings/clock/sifive-fu540-prci.h>



/ {

	#address-cells = <2>;

	#size-cells = <2>;

	compatible = "sifive,fu540-c000", "sifive,fu540";



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

	};



	chosen {

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		timebase-frequency = <1000000>;

		cpu0: cpu@0 {

			compatible = "sifive,e51", "sifive,rocket0", "riscv";

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <128>;

			i-cache-size = <16384>;

			reg = <0>;

			riscv,isa = "rv64imac";

			status = "disabled";

			cpu0_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				interrupt-controller;

			};

		};

		cpu1: cpu@1 {

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			reg = <1>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			cpu1_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				interrupt-controller;

			};

		};

		cpu2: cpu@2 {

			clock-frequency = <0>;

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			reg = <2>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			cpu2_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				interrupt-controller;

			};

		};

		cpu3: cpu@3 {

			clock-frequency = <0>;

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			reg = <3>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			cpu3_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				interrupt-controller;

			};

		};

		cpu4: cpu@4 {

			clock-frequency = <0>;

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			reg = <4>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			cpu4_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				interrupt-controller;

			};

		};

	};

	soc {

		#address-cells = <2>;

		#size-cells = <2>;

		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";

		ranges;

		plic0: interrupt-controller@c000000 {

			#interrupt-cells = <1>;

			compatible = "sifive,plic-1.0.0";

			reg = <0x0 0xc000000 0x0 0x4000000>;

			riscv,ndev = <53>;

			interrupt-controller;

			interrupts-extended = <

				&cpu0_intc 0xffffffff

				&cpu1_intc 0xffffffff &cpu1_intc 9

				&cpu2_intc 0xffffffff &cpu2_intc 9

				&cpu3_intc 0xffffffff &cpu3_intc 9

				&cpu4_intc 0xffffffff &cpu4_intc 9>;

		};

		prci: clock-controller@10000000 {

			compatible = "sifive,fu540-c000-prci";

			reg = <0x0 0x10000000 0x0 0x1000>;

			clocks = <&hfclk>, <&rtcclk>;

			#clock-cells = <1>;

		};

		uart0: serial@10010000 {

			compatible = "sifive,fu540-c000-uart", "sifive,uart0";

			reg = <0x0 0x10010000 0x0 0x1000>;

			interrupt-parent = <&plic0>;

			interrupts = <4>;

			clocks = <&prci PRCI_CLK_TLCLK>;

		};

		uart1: serial@10011000 {

			compatible = "sifive,fu540-c000-uart", "sifive,uart0";

			reg = <0x0 0x10011000 0x0 0x1000>;

			interrupt-parent = <&plic0>;

			interrupts = <5>;

			clocks = <&prci PRCI_CLK_TLCLK>;

		};

		i2c0: i2c@10030000 {

			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";

			reg = <0x0 0x10030000 0x0 0x1000>;

			interrupt-parent = <&plic0>;

			interrupts = <50>;

			clocks = <&prci PRCI_CLK_TLCLK>;

			reg-shift = <2>;

			reg-io-width = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

		qspi0: spi@10040000 {

			compatible = "sifive,fu540-c000-spi", "sifive,spi0";

			reg = <0x0 0x10040000 0x0 0x1000

			       0x0 0x20000000 0x0 0x10000000>;

			interrupt-parent = <&plic0>;

			interrupts = <51>;

			clocks = <&prci PRCI_CLK_TLCLK>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

		qspi1: spi@10041000 {

			compatible = "sifive,fu540-c000-spi", "sifive,spi0";

			reg = <0x0 0x10041000 0x0 0x1000

			       0x0 0x30000000 0x0 0x10000000>;

			interrupt-parent = <&plic0>;

			interrupts = <52>;

			clocks = <&prci PRCI_CLK_TLCLK>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

		qspi2: spi@10050000 {

			compatible = "sifive,fu540-c000-spi", "sifive,spi0";

			reg = <0x0 0x10050000 0x0 0x1000>;

			interrupt-parent = <&plic0>;

			interrupts = <6>;

			clocks = <&prci PRCI_CLK_TLCLK>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};

};

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