Commit 71f34979 authored by David Gibson's avatar David Gibson Committed by Josh Boyer
Browse files

[POWERPC] Convert remaining dts-v0 files to v1 



At the moment we have a mixture of left-over version 0 and new-format
version 1 files in arch/powerpc/boot/dts.  This is potentially
confusing to people new to the dts format attempting to figure it out.

So, this patch converts all the as-yet unconverted dts v0 files and
converts them to v1.  They're mechanically-converted, and not hand
tweaked so in some cases they're not 100% in keeping with usual v1
style, but the convertor program does have some heuristics so the
discrepancies aren't too bad.

I have checked that this patch produces no changes to the resulting
dtb binaries.

Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Acked-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: default avatarGeoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
parent b786af11

arch/powerpc/boot/dts/bamboo.dts

+72 −70
Original line number Diff line number Diff line
@@ -11,12 +11,14 @@ 
 * any warranty of any kind, whether express or implied.

 */



/dts-v1/;



/ {

	#address-cells = <2>;

	#size-cells = <1>;

	model = "amcc,bamboo";

	compatible = "amcc,bamboo";

	dcr-parent = <&/cpus/cpu@0>;

	dcr-parent = <&{/cpus/cpu@0}>;



	aliases {

		ethernet0 = &EMAC0;
@@ -34,13 +36,13 @@ 
		cpu@0 {

			device_type = "cpu";

			model = "PowerPC,440EP";

			reg = <0>;

			reg = <0x00000000>;

			clock-frequency = <0>; /* Filled in by zImage */

			timebase-frequency = <0>; /* Filled in by zImage */

			i-cache-line-size = <20>;

			d-cache-line-size = <20>;

			i-cache-size = <8000>;

			d-cache-size = <8000>;

			i-cache-line-size = <32>;

			d-cache-line-size = <32>;

			i-cache-size = <32768>;

			d-cache-size = <32768>;

			dcr-controller;

			dcr-access-method = "native";

		};
@@ -48,14 +50,14 @@ 


	memory {

		device_type = "memory";

		reg = <0 0 0>; /* Filled in by zImage */

		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */

	};



	UIC0: interrupt-controller0 {

		compatible = "ibm,uic-440ep","ibm,uic";

		interrupt-controller;

		cell-index = <0>;

		dcr-reg = <0c0 009>;

		dcr-reg = <0x0c0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;
@@ -65,22 +67,22 @@ 
		compatible = "ibm,uic-440ep","ibm,uic";

		interrupt-controller;

		cell-index = <1>;

		dcr-reg = <0d0 009>;

		dcr-reg = <0x0d0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;

		interrupts = <1e 4 1f 4>; /* cascade */

		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */

		interrupt-parent = <&UIC0>;

	};



	SDR0: sdr {

		compatible = "ibm,sdr-440ep";

		dcr-reg = <00e 002>;

		dcr-reg = <0x00e 0x002>;

	};



	CPR0: cpr {

		compatible = "ibm,cpr-440ep";

		dcr-reg = <00c 002>;

		dcr-reg = <0x00c 0x002>;

	};



	plb {
@@ -92,29 +94,29 @@ 


		SDRAM0: sdram {

			compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";

			dcr-reg = <010 2>;

			dcr-reg = <0x010 0x002>;

		};



		DMA0: dma {

			compatible = "ibm,dma-440ep", "ibm,dma-440gp";

			dcr-reg = <100 027>;

			dcr-reg = <0x100 0x027>;

		};



		MAL0: mcmal {

			compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";

			dcr-reg = <180 62>;

			dcr-reg = <0x180 0x062>;

			num-tx-chans = <4>;

			num-rx-chans = <2>;

			interrupt-parent = <&MAL0>;

			interrupts = <0 1 2 3 4>;

			interrupts = <0x0 0x1 0x2 0x3 0x4>;

			#interrupt-cells = <1>;

			#address-cells = <0>;

			#size-cells = <0>;

			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4

					/*RXEOB*/ 1 &UIC0 b 4

					/*SERR*/  2 &UIC1 0 4

					/*TXDE*/  3 &UIC1 1 4

					/*RXDE*/  4 &UIC1 2 4>;

			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4

					/*RXEOB*/ 0x1 &UIC0 0xb 0x4

					/*SERR*/  0x2 &UIC1 0x0 0x4

					/*TXDE*/  0x3 &UIC1 0x1 0x4

					/*RXDE*/  0x4 &UIC1 0x2 0x4>;

		};



		POB0: opb {
@@ -124,101 +126,101 @@ 
			/* Bamboo is oddball in the 44x world and doesn't use the ERPN

			 * bits.

			 */

		  	ranges = <00000000 0 00000000 80000000

			          80000000 0 80000000 80000000>;

		  	ranges = <0x00000000 0x00000000 0x00000000 0x80000000

			          0x80000000 0x00000000 0x80000000 0x80000000>;

		  	interrupt-parent = <&UIC1>;

		  	interrupts = <7 4>;

		  	interrupts = <0x7 0x4>;

		  	clock-frequency = <0>; /* Filled in by zImage */



			EBC0: ebc {

				compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";

				dcr-reg = <012 2>;

				dcr-reg = <0x012 0x002>;

				#address-cells = <2>;

				#size-cells = <1>;

				clock-frequency = <0>; /* Filled in by zImage */

				interrupts = <5 1>;

				interrupts = <0x5 0x1>;

				interrupt-parent = <&UIC1>;

			};



			UART0: serial@ef600300 {

		   		device_type = "serial";

		   		compatible = "ns16550";

		   		reg = <ef600300 8>;

		   		virtual-reg = <ef600300>;

		   		reg = <0xef600300 0x00000008>;

		   		virtual-reg = <0xef600300>;

		   		clock-frequency = <0>; /* Filled in by zImage */

		   		current-speed = <1c200>;

		   		current-speed = <115200>;

		   		interrupt-parent = <&UIC0>;

		   		interrupts = <0 4>;

		   		interrupts = <0x0 0x4>;

	   		};



			UART1: serial@ef600400 {

		   		device_type = "serial";

		   		compatible = "ns16550";

		   		reg = <ef600400 8>;

		   		virtual-reg = <ef600400>;

		   		reg = <0xef600400 0x00000008>;

		   		virtual-reg = <0xef600400>;

		   		clock-frequency = <0>;

		   		current-speed = <0>;

		   		interrupt-parent = <&UIC0>;

		   		interrupts = <1 4>;

		   		interrupts = <0x1 0x4>;

	   		};



			UART2: serial@ef600500 {

		   		device_type = "serial";

		   		compatible = "ns16550";

		   		reg = <ef600500 8>;

		   		virtual-reg = <ef600500>;

		   		reg = <0xef600500 0x00000008>;

		   		virtual-reg = <0xef600500>;

		   		clock-frequency = <0>;

		   		current-speed = <0>;

		   		interrupt-parent = <&UIC0>;

		   		interrupts = <3 4>;

		   		interrupts = <0x3 0x4>;

	   		};



			UART3: serial@ef600600 {

		   		device_type = "serial";

		   		compatible = "ns16550";

		   		reg = <ef600600 8>;

		   		virtual-reg = <ef600600>;

		   		reg = <0xef600600 0x00000008>;

		   		virtual-reg = <0xef600600>;

		   		clock-frequency = <0>;

		   		current-speed = <0>;

		   		interrupt-parent = <&UIC0>;

		   		interrupts = <4 4>;

		   		interrupts = <0x4 0x4>;

	   		};



			IIC0: i2c@ef600700 {

				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";

				reg = <ef600700 14>;

				reg = <0xef600700 0x00000014>;

				interrupt-parent = <&UIC0>;

				interrupts = <2 4>;

				interrupts = <0x2 0x4>;

			};



			IIC1: i2c@ef600800 {

				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";

				reg = <ef600800 14>;

				reg = <0xef600800 0x00000014>;

				interrupt-parent = <&UIC0>;

				interrupts = <7 4>;

				interrupts = <0x7 0x4>;

			};



			ZMII0: emac-zmii@ef600d00 {

				compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";

				reg = <ef600d00 c>;

				reg = <0xef600d00 0x0000000c>;

			};



			EMAC0: ethernet@ef600e00 {

				device_type = "network";

				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";

				interrupt-parent = <&UIC1>;

				interrupts = <1c 4 1d 4>;

				reg = <ef600e00 70>;

				interrupts = <0x1c 0x4 0x1d 0x4>;

				reg = <0xef600e00 0x00000070>;

				local-mac-address = [000000000000];

				mal-device = <&MAL0>;

				mal-tx-channel = <0 1>;

				mal-rx-channel = <0>;

				cell-index = <0>;

				max-frame-size = <5dc>;

				rx-fifo-size = <1000>;

				tx-fifo-size = <800>;

				max-frame-size = <1500>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				phy-mode = "rmii";

				phy-map = <00000000>;

				phy-map = <0x00000000>;

				zmii-device = <&ZMII0>;

				zmii-channel = <0>;

			};
@@ -227,26 +229,26 @@ 
				device_type = "network";

				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";

				interrupt-parent = <&UIC1>;

				interrupts = <1e 4 1f 4>;

				reg = <ef600f00 70>;

				interrupts = <0x1e 0x4 0x1f 0x4>;

				reg = <0xef600f00 0x00000070>;

				local-mac-address = [000000000000];

				mal-device = <&MAL0>;

				mal-tx-channel = <2 3>;

				mal-rx-channel = <1>;

				cell-index = <1>;

				max-frame-size = <5dc>;

				rx-fifo-size = <1000>;

				tx-fifo-size = <800>;

				max-frame-size = <1500>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				phy-mode = "rmii";

				phy-map = <00000000>;

				phy-map = <0x00000000>;

				zmii-device = <&ZMII0>;

				zmii-channel = <1>;

			};



			usb@ef601000 {

				compatible = "ohci-be";

				reg = <ef601000 80>;

				interrupts = <8 1 9 1>;

				reg = <0xef601000 0x00000080>;

				interrupts = <0x8 0x1 0x9 0x1>;

				interrupt-parent = < &UIC1 >;

			};

		};
@@ -258,35 +260,35 @@ 
			#address-cells = <3>;

			compatible = "ibm,plb440ep-pci", "ibm,plb-pci";

			primary;

			reg = <0 eec00000 8	/* Config space access */

			       0 eed00000 4	/* IACK */

			       0 eed00000 4	/* Special cycle */

			       0 ef400000 40>;	/* Internal registers */

			reg = <0x00000000 0xeec00000 0x00000008	/* Config space access */

			       0x00000000 0xeed00000 0x00000004	/* IACK */

			       0x00000000 0xeed00000 0x00000004	/* Special cycle */

			       0x00000000 0xef400000 0x00000040>;	/* Internal registers */



			/* Outbound ranges, one memory and one IO,

			 * later cannot be changed. Chip supports a second

			 * IO range but we don't use it for now

			 */

			ranges = <02000000 0 a0000000 0 a0000000 0 20000000

				  01000000 0 00000000 0 e8000000 0 00010000>;

			ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000

				  0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;



			/* Inbound 2GB range starting at 0 */

			dma-ranges = <42000000 0 0 0 0 0 80000000>;

			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;



			/* Bamboo has all 4 IRQ pins tied together per slot */

			interrupt-map-mask = <f800 0 0 0>;

			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;

			interrupt-map = <

				/* IDSEL 1 */

				0800 0 0 0 &UIC0 1c 8

				0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8



				/* IDSEL 2 */

				1000 0 0 0 &UIC0 1b 8

				0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8



				/* IDSEL 3 */

				1800 0 0 0 &UIC0 1a 8

				0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8



				/* IDSEL 4 */

				2000 0 0 0 &UIC0 19 8

				0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8

			>;

		};

	};

arch/powerpc/boot/dts/canyonlands.dts

+112 −110
Original line number Diff line number Diff line
@@ -8,12 +8,14 @@ 
 * any warranty of any kind, whether express or implied.

 */



/dts-v1/;



/ {

	#address-cells = <2>;

	#size-cells = <1>;

	model = "amcc,canyonlands";

	compatible = "amcc,canyonlands";

	dcr-parent = <&/cpus/cpu@0>;

	dcr-parent = <&{/cpus/cpu@0}>;



	aliases {

		ethernet0 = &EMAC0;
@@ -29,13 +31,13 @@ 
		cpu@0 {

			device_type = "cpu";

			model = "PowerPC,460EX";

			reg = <0>;

			reg = <0x00000000>;

			clock-frequency = <0>; /* Filled in by U-Boot */

			timebase-frequency = <0>; /* Filled in by U-Boot */

			i-cache-line-size = <20>;

			d-cache-line-size = <20>;

			i-cache-size = <8000>;

			d-cache-size = <8000>;

			i-cache-line-size = <32>;

			d-cache-line-size = <32>;

			i-cache-size = <32768>;

			d-cache-size = <32768>;

			dcr-controller;

			dcr-access-method = "native";

		};
@@ -43,14 +45,14 @@ 


	memory {

		device_type = "memory";

		reg = <0 0 0>; /* Filled in by U-Boot */

		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */

	};



	UIC0: interrupt-controller0 {

		compatible = "ibm,uic-460ex","ibm,uic";

		interrupt-controller;

		cell-index = <0>;

		dcr-reg = <0c0 009>;

		dcr-reg = <0x0c0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;
@@ -60,11 +62,11 @@ 
		compatible = "ibm,uic-460ex","ibm,uic";

		interrupt-controller;

		cell-index = <1>;

		dcr-reg = <0d0 009>;

		dcr-reg = <0x0d0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;

		interrupts = <1e 4 1f 4>; /* cascade */

		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */

		interrupt-parent = <&UIC0>;

	};
@@ -72,11 +74,11 @@ 
		compatible = "ibm,uic-460ex","ibm,uic";

		interrupt-controller;

		cell-index = <2>;

		dcr-reg = <0e0 009>;

		dcr-reg = <0x0e0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;

		interrupts = <a 4 b 4>; /* cascade */

		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */

		interrupt-parent = <&UIC0>;

	};
@@ -84,22 +86,22 @@ 
		compatible = "ibm,uic-460ex","ibm,uic";

		interrupt-controller;

		cell-index = <3>;

		dcr-reg = <0f0 009>;

		dcr-reg = <0x0f0 0x009>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;

		interrupts = <10 4 11 4>; /* cascade */

		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */

		interrupt-parent = <&UIC0>;

	};



	SDR0: sdr {

		compatible = "ibm,sdr-460ex";

		dcr-reg = <00e 002>;

		dcr-reg = <0x00e 0x002>;

	};



	CPR0: cpr {

		compatible = "ibm,cpr-460ex";

		dcr-reg = <00c 002>;

		dcr-reg = <0x00c 0x002>;

	};



	plb {
@@ -111,74 +113,74 @@ 


		SDRAM0: sdram {

			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";

			dcr-reg = <010 2>;

			dcr-reg = <0x010 0x002>;

		};



		MAL0: mcmal {

			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";

			dcr-reg = <180 62>;

			dcr-reg = <0x180 0x062>;

			num-tx-chans = <2>;

			num-rx-chans = <10>;

			num-rx-chans = <16>;

			#address-cells = <0>;

			#size-cells = <0>;

			interrupt-parent = <&UIC2>;

			interrupts = <	/*TXEOB*/ 6 4

					/*RXEOB*/ 7 4

					/*SERR*/  3 4

					/*TXDE*/  4 4

					/*RXDE*/  5 4>;

			interrupts = <	/*TXEOB*/ 0x6 0x4

					/*RXEOB*/ 0x7 0x4

					/*SERR*/  0x3 0x4

					/*TXDE*/  0x4 0x4

					/*RXDE*/  0x5 0x4>;

		};



		POB0: opb {

			compatible = "ibm,opb-460ex", "ibm,opb";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <b0000000 4 b0000000 50000000>;

			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;

			clock-frequency = <0>; /* Filled in by U-Boot */



			EBC0: ebc {

				compatible = "ibm,ebc-460ex", "ibm,ebc";

				dcr-reg = <012 2>;

				dcr-reg = <0x012 0x002>;

				#address-cells = <2>;

				#size-cells = <1>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				/* ranges property is supplied by U-Boot */

				interrupts = <6 4>;

				interrupts = <0x6 0x4>;

				interrupt-parent = <&UIC1>;



				nor_flash@0,0 {

					compatible = "amd,s29gl512n", "cfi-flash";

					bank-width = <2>;

					reg = <0 000000 4000000>;

					reg = <0x00000000 0x00000000 0x04000000>;

					#address-cells = <1>;

					#size-cells = <1>;

					partition@0 {

						label = "kernel";

						reg = <0 1e0000>;

						reg = <0x00000000 0x001e0000>;

					};

					partition@1e0000 {

						label = "dtb";

						reg = <1e0000 20000>;

						reg = <0x001e0000 0x00020000>;

					};

					partition@200000 {

						label = "ramdisk";

						reg = <200000 1400000>;

						reg = <0x00200000 0x01400000>;

					};

					partition@1600000 {

						label = "jffs2";

						reg = <1600000 400000>;

						reg = <0x01600000 0x00400000>;

					};

					partition@1a00000 {

						label = "user";

						reg = <1a00000 2560000>;

						reg = <0x01a00000 0x02560000>;

					};

					partition@3f60000 {

						label = "env";

						reg = <3f60000 40000>;

						reg = <0x03f60000 0x00040000>;

					};

					partition@3fa0000 {

						label = "u-boot";

						reg = <3fa0000 60000>;

						reg = <0x03fa0000 0x00060000>;

					};

				};

			};
@@ -186,103 +188,103 @@ 
			UART0: serial@ef600300 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <ef600300 8>;

				virtual-reg = <ef600300>;

				reg = <0xef600300 0x00000008>;

				virtual-reg = <0xef600300>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC1>;

				interrupts = <1 4>;

				interrupts = <0x1 0x4>;

			};



			UART1: serial@ef600400 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <ef600400 8>;

				virtual-reg = <ef600400>;

				reg = <0xef600400 0x00000008>;

				virtual-reg = <0xef600400>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC0>;

				interrupts = <1 4>;

				interrupts = <0x1 0x4>;

			};



			UART2: serial@ef600500 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <ef600500 8>;

				virtual-reg = <ef600500>;

				reg = <0xef600500 0x00000008>;

				virtual-reg = <0xef600500>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC1>;

				interrupts = <1d 4>;

				interrupts = <0x1d 0x4>;

			};



			UART3: serial@ef600600 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <ef600600 8>;

				virtual-reg = <ef600600>;

				reg = <0xef600600 0x00000008>;

				virtual-reg = <0xef600600>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC1>;

				interrupts = <1e 4>;

				interrupts = <0x1e 0x4>;

			};



			IIC0: i2c@ef600700 {

				compatible = "ibm,iic-460ex", "ibm,iic";

				reg = <ef600700 14>;

				reg = <0xef600700 0x00000014>;

				interrupt-parent = <&UIC0>;

				interrupts = <2 4>;

				interrupts = <0x2 0x4>;

			};



			IIC1: i2c@ef600800 {

				compatible = "ibm,iic-460ex", "ibm,iic";

				reg = <ef600800 14>;

				reg = <0xef600800 0x00000014>;

				interrupt-parent = <&UIC0>;

				interrupts = <3 4>;

				interrupts = <0x3 0x4>;

			};



			ZMII0: emac-zmii@ef600d00 {

				compatible = "ibm,zmii-460ex", "ibm,zmii";

				reg = <ef600d00 c>;

				reg = <0xef600d00 0x0000000c>;

			};



			RGMII0: emac-rgmii@ef601500 {

				compatible = "ibm,rgmii-460ex", "ibm,rgmii";

				reg = <ef601500 8>;

				reg = <0xef601500 0x00000008>;

				has-mdio;

			};



			TAH0: emac-tah@ef601350 {

				compatible = "ibm,tah-460ex", "ibm,tah";

				reg = <ef601350 30>;

				reg = <0xef601350 0x00000030>;

			};



			TAH1: emac-tah@ef601450 {

				compatible = "ibm,tah-460ex", "ibm,tah";

				reg = <ef601450 30>;

				reg = <0xef601450 0x00000030>;

			};



			EMAC0: ethernet@ef600e00 {

				device_type = "network";

				compatible = "ibm,emac-460ex", "ibm,emac4";

				interrupt-parent = <&EMAC0>;

				interrupts = <0 1>;

				interrupts = <0x0 0x1>;

				#interrupt-cells = <1>;

				#address-cells = <0>;

				#size-cells = <0>;

				interrupt-map = </*Status*/ 0 &UIC2 10 4

						 /*Wake*/   1 &UIC2 14 4>;

				reg = <ef600e00 70>;

				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4

						 /*Wake*/   0x1 &UIC2 0x14 0x4>;

				reg = <0xef600e00 0x00000070>;

				local-mac-address = [000000000000]; /* Filled in by U-Boot */

				mal-device = <&MAL0>;

				mal-tx-channel = <0>;

				mal-rx-channel = <0>;

				cell-index = <0>;

				max-frame-size = <2328>;

				rx-fifo-size = <1000>;

				tx-fifo-size = <800>;

				max-frame-size = <9000>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				phy-mode = "rgmii";

				phy-map = <00000000>;

				phy-map = <0x00000000>;

				rgmii-device = <&RGMII0>;

				rgmii-channel = <0>;

				tah-device = <&TAH0>;
@@ -295,23 +297,23 @@ 
				device_type = "network";

				compatible = "ibm,emac-460ex", "ibm,emac4";

				interrupt-parent = <&EMAC1>;

				interrupts = <0 1>;

				interrupts = <0x0 0x1>;

				#interrupt-cells = <1>;

				#address-cells = <0>;

				#size-cells = <0>;

				interrupt-map = </*Status*/ 0 &UIC2 11 4

						 /*Wake*/   1 &UIC2 15 4>;

				reg = <ef600f00 70>;

				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4

						 /*Wake*/   0x1 &UIC2 0x15 0x4>;

				reg = <0xef600f00 0x00000070>;

				local-mac-address = [000000000000]; /* Filled in by U-Boot */

				mal-device = <&MAL0>;

				mal-tx-channel = <1>;

				mal-rx-channel = <8>;

				cell-index = <1>;

				max-frame-size = <2328>;

				rx-fifo-size = <1000>;

				tx-fifo-size = <800>;

				max-frame-size = <9000>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				phy-mode = "rgmii";

				phy-map = <00000000>;

				phy-map = <0x00000000>;

				rgmii-device = <&RGMII0>;

				rgmii-channel = <1>;

				tah-device = <&TAH1>;
@@ -331,27 +333,27 @@ 
			primary;

			large-inbound-windows;

			enable-msi-hole;

			reg = <c 0ec00000   8	/* Config space access */

			       0 0 0		/* no IACK cycles */

			       c 0ed00000   4   /* Special cycles */

			       c 0ec80000 100	/* Internal registers */

			       c 0ec80100  fc>;	/* Internal messaging registers */

			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */

			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */

			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */

			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */

			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */



			/* Outbound ranges, one memory and one IO,

			 * later cannot be changed

			 */

			ranges = <02000000 0 80000000 0000000d 80000000 0 80000000

				  01000000 0 00000000 0000000c 08000000 0 00010000>;

			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000

				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;



			/* Inbound 2GB range starting at 0 */

			dma-ranges = <42000000 0 0 0 0 0 80000000>;

			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;



			/* This drives busses 0 to 0x3f */

			bus-range = <0 3f>;

			bus-range = <0x0 0x3f>;



			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */

			interrupt-map-mask = <0000 0 0 0>;

			interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;

			interrupt-map-mask = <0x0 0x0 0x0 0x0>;

			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;

		};



		PCIE0: pciex@d00000000 {
@@ -361,23 +363,23 @@ 
			#address-cells = <3>;

			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";

			primary;

			port = <0>; /* port number */

			reg = <d 00000000 20000000	/* Config space access */

			       c 08010000 00001000>;	/* Registers */

			dcr-reg = <100 020>;

			sdr-base = <300>;

			port = <0x0>; /* port number */

			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */

			       0x0000000c 0x08010000 0x00001000>;	/* Registers */

			dcr-reg = <0x100 0x020>;

			sdr-base = <0x300>;



			/* Outbound ranges, one memory and one IO,

			 * later cannot be changed

			 */

			ranges = <02000000 0 80000000 0000000e 00000000 0 80000000

				  01000000 0 00000000 0000000f 80000000 0 00010000>;

			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000

				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;



			/* Inbound 2GB range starting at 0 */

			dma-ranges = <42000000 0 0 0 0 0 80000000>;

			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;



			/* This drives busses 40 to 0x7f */

			bus-range = <40 7f>;

			bus-range = <0x40 0x7f>;



			/* Legacy interrupts (note the weird polarity, the bridge seems

			 * to invert PCIe legacy interrupts).
@@ -387,12 +389,12 @@ 
			 * below are basically de-swizzled numbers.

			 * The real slot is on idsel 0, so the swizzling is 1:1

			 */

			interrupt-map-mask = <0000 0 0 7>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <

				0000 0 0 1 &UIC3 c 4 /* swizzled int A */

				0000 0 0 2 &UIC3 d 4 /* swizzled int B */

				0000 0 0 3 &UIC3 e 4 /* swizzled int C */

				0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;

				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */

				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */

				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */

				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;

		};



		PCIE1: pciex@d20000000 {
@@ -402,23 +404,23 @@ 
			#address-cells = <3>;

			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";

			primary;

			port = <1>; /* port number */

			reg = <d 20000000 20000000	/* Config space access */

			       c 08011000 00001000>;	/* Registers */

			dcr-reg = <120 020>;

			sdr-base = <340>;

			port = <0x1>; /* port number */

			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */

			       0x0000000c 0x08011000 0x00001000>;	/* Registers */

			dcr-reg = <0x120 0x020>;

			sdr-base = <0x340>;



			/* Outbound ranges, one memory and one IO,

			 * later cannot be changed

			 */

			ranges = <02000000 0 80000000 0000000e 80000000 0 80000000

				  01000000 0 00000000 0000000f 80010000 0 00010000>;

			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000

				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;



			/* Inbound 2GB range starting at 0 */

			dma-ranges = <42000000 0 0 0 0 0 80000000>;

			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;



			/* This drives busses 80 to 0xbf */

			bus-range = <80 bf>;

			bus-range = <0x80 0xbf>;



			/* Legacy interrupts (note the weird polarity, the bridge seems

			 * to invert PCIe legacy interrupts).
@@ -428,12 +430,12 @@ 
			 * below are basically de-swizzled numbers.

			 * The real slot is on idsel 0, so the swizzling is 1:1

			 */

			interrupt-map-mask = <0000 0 0 7>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <

				0000 0 0 1 &UIC3 10 4 /* swizzled int A */

				0000 0 0 2 &UIC3 11 4 /* swizzled int B */

				0000 0 0 3 &UIC3 12 4 /* swizzled int C */

				0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;

				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */

				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */

				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */

				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;

		};

	};

};

arch/powerpc/boot/dts/ebony.dts

+83 −81

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arch/powerpc/boot/dts/ep405.dts

+51 −49

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arch/powerpc/boot/dts/glacier.dts

+132 −130

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