Commit 71b81f12 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: decouple global lock out of pipe control lock 



[why]
hwss should not guess what type of pipe lock is needed.
The caller of the lock function should know
the right type of pipe lock.
Decouple the setup of global lock outside of pipe control lock
logic.

Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 28e7a7f4

drivers/gpu/drm/amd/display/dc/core/dc.c

+20 −0
Original line number Diff line number Diff line
@@ -2220,6 +2220,11 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable)

			top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(

					top_pipe_to_program->stream_res.tg);



	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)

		dc->hwss.interdependent_update_lock(dc, context, true);

	else
@@ -2377,6 +2382,21 @@ static void commit_planes_for_stream(struct dc *dc, 
	else

		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);



	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

					top_pipe_to_program->stream_res.tg,

					CRTC_STATE_VACTIVE);

			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

					top_pipe_to_program->stream_res.tg,

					CRTC_STATE_VBLANK);

			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

					top_pipe_to_program->stream_res.tg,

					CRTC_STATE_VACTIVE);

			top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(

					top_pipe_to_program->stream_res.tg);

		}



	if (update_type != UPDATE_TYPE_FAST)

		dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+0 −27
Original line number Diff line number Diff line
@@ -1094,7 +1094,6 @@ void dcn20_pipe_control_lock( 
	bool lock)

{

	bool flip_immediate = false;

	bool dig_update_required = false;



	/* use TG master update lock to lock everything on the TG

	 * therefore only top pipe need to lock
@@ -1132,19 +1131,6 @@ void dcn20_pipe_control_lock( 
		    (!flip_immediate && pipe->stream_res.gsl_group > 0))

			dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);



	if (pipe->stream && pipe->stream->update_flags.bits.dsc_changed)

		dig_update_required = true;



	/* Need double buffer lock mode in order to synchronize front end pipe

	 * updates with dig updates.

	 */

	if (dig_update_required) {

		if (lock) {

			pipe->stream_res.tg->funcs->lock_doublebuffer_enable(

					pipe->stream_res.tg);

		}

	}



	if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

		if (lock)

			pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
@@ -1156,19 +1142,6 @@ void dcn20_pipe_control_lock( 
		else

			pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

	}



	if (dig_update_required) {

		if (!lock) {

			pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,

					CRTC_STATE_VACTIVE);

			pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,

					CRTC_STATE_VBLANK);

			pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,

					CRTC_STATE_VACTIVE);

			pipe->stream_res.tg->funcs->lock_doublebuffer_disable(

					pipe->stream_res.tg);

		}

	}

}



static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)

CRA Git | Maintained and supported by SUSTech CRA and CCSE