Commit 71776b6d authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup mtype mapping 



Unify how we map the UAPI flags to the PTE hardware flags for a mapping.

Only the MTYPE is actually ASIC dependent, all other flags should be
copied over 1 to 1 and ASIC differences are handled later on.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1dd077bb

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+1 −1
Original line number Diff line number Diff line
@@ -381,7 +381,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) 
			AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;

	}



	return amdgpu_gmc_get_pte_flags(adev, mapping_flags);

	return amdgpu_gem_va_map_flags(adev, mapping_flags);

}



/* add_bo_to_vm - Add a BO to a VM

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+30 −2
Original line number Diff line number Diff line
@@ -532,6 +532,34 @@ error: 
		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);

}



/**

 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags

 *

 * @adev: amdgpu_device pointer

 * @flags: GEM UAPI flags

 *

 * Returns the GEM UAPI flags mapped into hardware for the ASIC.

 */

uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)

{

	uint64_t pte_flag = 0;



	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)

		pte_flag |= AMDGPU_PTE_EXECUTABLE;

	if (flags & AMDGPU_VM_PAGE_READABLE)

		pte_flag |= AMDGPU_PTE_READABLE;

	if (flags & AMDGPU_VM_PAGE_WRITEABLE)

		pte_flag |= AMDGPU_PTE_WRITEABLE;

	if (flags & AMDGPU_VM_PAGE_PRT)

		pte_flag |= AMDGPU_PTE_PRT;



	if (adev->gmc.gmc_funcs->map_mtype)

		pte_flag |= amdgpu_gmc_map_mtype(adev,

						 flags & AMDGPU_VM_MTYPE_MASK);



	return pte_flag;

}



int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,

			  struct drm_file *filp)

{
@@ -629,7 +657,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 


	switch (args->operation) {

	case AMDGPU_VA_OP_MAP:

		va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);

		va_flags = amdgpu_gem_va_map_flags(adev, args->flags);

		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,

				     args->offset_in_bo, args->map_size,

				     va_flags);
@@ -644,7 +672,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 
						args->map_size);

		break;

	case AMDGPU_VA_OP_REPLACE:

		va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);

		va_flags = amdgpu_gem_va_map_flags(adev, args->flags);

		r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,

					     args->offset_in_bo, args->map_size,

					     va_flags);

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 
			  struct drm_file *filp);

int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,

			      struct drm_file *filp);

uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags);

int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,

			  struct drm_file *filp);

int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+3 −4
Original line number Diff line number Diff line
@@ -99,9 +99,8 @@ struct amdgpu_gmc_funcs { 
				   unsigned pasid);

	/* enable/disable PRT support */

	void (*set_prt)(struct amdgpu_device *adev, bool enable);

	/* set pte flags based per asic */

	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,

				     uint32_t flags);

	/* map mtype to hardware flags */

	uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);

	/* get the pde for a given mc addr */

	void (*get_vm_pde)(struct amdgpu_device *adev, int level,

			   u64 *dst, u64 *flags);
@@ -184,8 +183,8 @@ struct amdgpu_gmc { 
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))

#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))

#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))

#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))

#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))

#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))



/**

 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+4 −2
Original line number Diff line number Diff line
@@ -1571,8 +1571,10 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, 
	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))

		flags &= ~AMDGPU_PTE_WRITEABLE;



	if (adev->asic_type >= CHIP_TONGA) {

		flags &= ~AMDGPU_PTE_EXECUTABLE;

		flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;

	}



	if (adev->asic_type >= CHIP_NAVI10) {

		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;

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