Merge tag 'kvm_mips_4.12_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips

corresponds to guest physical address zero.  Use of mmap() on a VM fd

is discouraged if userspace memory allocation (KVM_CAP_USER_MEMORY) is

available.

You most certainly want to use 0 as machine type.

You probably want to use 0 as machine type.

In order to create user controlled virtual machines on S390, check

KVM_CAP_S390_UCONTROL and use the flag KVM_VM_S390_UCONTROL as

privileged user (CAP_SYS_ADMIN).

To use hardware assisted virtualization on MIPS (VZ ASE) rather than

the default trap & emulate implementation (which changes the virtual

memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the

flag KVM_VM_MIPS_VZ.

4.3 KVM_GET_MSR_INDEX_LIST

  MIPS  | KVM_REG_MIPS_CP0_ENTRYLO0     | 64

  MIPS  | KVM_REG_MIPS_CP0_ENTRYLO1     | 64

  MIPS  | KVM_REG_MIPS_CP0_CONTEXT      | 64

  MIPS  | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32

  MIPS  | KVM_REG_MIPS_CP0_USERLOCAL    | 64

  MIPS  | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64

  MIPS  | KVM_REG_MIPS_CP0_PAGEMASK     | 32

  MIPS  | KVM_REG_MIPS_CP0_PAGEGRAIN    | 32

  MIPS  | KVM_REG_MIPS_CP0_SEGCTL0      | 64

  MIPS  | KVM_REG_MIPS_CP0_SEGCTL1      | 64

  MIPS  | KVM_REG_MIPS_CP0_SEGCTL2      | 64

  MIPS  | KVM_REG_MIPS_CP0_PWBASE       | 64

  MIPS  | KVM_REG_MIPS_CP0_PWFIELD      | 64

  MIPS  | KVM_REG_MIPS_CP0_PWSIZE       | 64

  MIPS  | KVM_REG_MIPS_CP0_WIRED        | 32

  MIPS  | KVM_REG_MIPS_CP0_PWCTL        | 32

  MIPS  | KVM_REG_MIPS_CP0_HWRENA       | 32

  MIPS  | KVM_REG_MIPS_CP0_BADVADDR     | 64

  MIPS  | KVM_REG_MIPS_CP0_BADINSTR     | 32

  MIPS  | KVM_REG_MIPS_CP0_BADINSTRP    | 32

  MIPS  | KVM_REG_MIPS_CP0_COUNT        | 32

  MIPS  | KVM_REG_MIPS_CP0_ENTRYHI      | 64

  MIPS  | KVM_REG_MIPS_CP0_COMPARE      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG4      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG5      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG7      | 32

  MIPS  | KVM_REG_MIPS_CP0_XCONTEXT     | 64

  MIPS  | KVM_REG_MIPS_CP0_ERROREPC     | 64

  MIPS  | KVM_REG_MIPS_CP0_KSCRATCH1    | 64

  MIPS  | KVM_REG_MIPS_CP0_KSCRATCH2    | 64

  MIPS  | KVM_REG_MIPS_CP0_KSCRATCH4    | 64

  MIPS  | KVM_REG_MIPS_CP0_KSCRATCH5    | 64

  MIPS  | KVM_REG_MIPS_CP0_KSCRATCH6    | 64

  MIPS  | KVM_REG_MIPS_CP0_MAAR(0..63)  | 64

  MIPS  | KVM_REG_MIPS_COUNT_CTL        | 64

  MIPS  | KVM_REG_MIPS_COUNT_RESUME     | 64

  MIPS  | KVM_REG_MIPS_COUNT_HZ         | 64

with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and

the PFNX field starting at bit 30.

MIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit

patterns:

  0x7030 0000 0001 01 <reg:8>

MIPS KVM control registers (see above) have the following id bit patterns:

  0x7030 0000 0002 <reg:16>

available, means that that the kernel can support guests using the

hashed page table MMU defined in Power ISA V3.00 (as implemented in

the POWER9 processor), including in-memory segment tables.

8.5 KVM_CAP_MIPS_VZ

Architectures: mips

This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that

it is available, means that full hardware assisted virtualization capabilities

of the hardware are available for use through KVM. An appropriate

KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which

utilises it.

If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is

available, it means that the VM is using full hardware assisted virtualization

capabilities of the hardware. This is useful to check after creating a VM with

KVM_VM_MIPS_DEFAULT.

The value returned by KVM_CHECK_EXTENSION should be compared against known

values (see below). All other values are reserved. This is to allow for the

possibility of other hardware assisted virtualization implementations which

may be incompatible with the MIPS VZ ASE.

 0: The trap & emulate implementation is in use to run guest code in user

    mode. Guest virtual memory segments are rearranged to fit the guest in the

    user mode address space.

 1: The MIPS VZ ASE is in use, providing full hardware assisted

    virtualization, including standard guest virtual memory segments.

8.6 KVM_CAP_MIPS_TE

Architectures: mips

This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that

it is available, means that the trap & emulate implementation is available to

run guest code in user mode, even if KVM_CAP_MIPS_VZ indicates that hardware

assisted virtualisation is also available. KVM_VM_MIPS_TE (0) must be passed

to KVM_CREATE_VM to create a VM which utilises it.

If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is

available, it means that the VM is using trap & emulate.

8.7 KVM_CAP_MIPS_64BIT

Architectures: mips

This capability indicates the supported architecture type of the guest, i.e. the

supported register and address width.

The values returned when this capability is checked by KVM_CHECK_EXTENSION on a

kvm VM handle correspond roughly to the CP0_Config.AT register field, and should

be checked specifically against known values (see below). All other values are

reserved.

 0: MIPS32 or microMIPS32.

    Both registers and addresses are 32-bits wide.

    It will only be possible to run 32-bit guest code.

 1: MIPS64 or microMIPS64 with access only to 32-bit compatibility segments.

    Registers are 64-bits wide, but addresses are 32-bits wide.

    64-bit guest code may run but cannot access MIPS64 memory segments.

    It will also be possible to run 32-bit guest code.

 2: MIPS64 or microMIPS64 with access to all address segments.

    Both registers and addresses are 64-bits wide.

    It will be possible to run 64-bit or 32-bit guest code.

  property inside the device tree's /hypervisor node.

  For more information refer to Documentation/virtual/kvm/ppc-pv.txt

MIPS:

  KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall

  number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and

  the return value is placed in $2 (v0).

KVM Hypercalls Documentation

===========================

The template for each hypercall is:

	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN

	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN

	select MIPS_L1_CACHE_SHIFT_7

	select HAVE_KVM

	help

	  The Cavium Octeon processor is a highly integrated chip containing

	  many ethernet hardware widgets for networking tasks. The processor

# define cpu_has_msa		0

#endif

#ifndef cpu_has_ufr

# define cpu_has_ufr		(cpu_data[0].options & MIPS_CPU_UFR)

#endif

#ifndef cpu_has_fre

# define cpu_has_fre		(cpu_data[0].options & MIPS_CPU_FRE)

#endif

#ifndef cpu_guest_has_htw

#define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)

#endif

#ifndef cpu_guest_has_mvh

#define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)

#endif

#ifndef cpu_guest_has_msa

#define cpu_guest_has_msa	(cpu_data[0].guest.ases & MIPS_ASE_MSA)

#endif

#ifndef cpu_guest_has_maar

#define cpu_guest_has_maar	(cpu_data[0].guest.options & MIPS_CPU_MAAR)

#endif

#ifndef cpu_guest_has_userlocal

#define cpu_guest_has_userlocal	(cpu_data[0].guest.options & MIPS_CPU_ULRI)

#endif

/*

 * Guest dynamic capabilities

	unsigned long		ases_dyn;

	unsigned long long	options;

	unsigned long long	options_dyn;

	int			tlbsize;

	u8			conf;

	u8			kscratch_mask;

};

	struct guest_info	guest;

	unsigned int		gtoffset_mask;

	unsigned int		guestid_mask;

	unsigned int		guestid_cache;

} __attribute__((aligned(SMP_CACHE_BYTES)));

extern struct cpuinfo_mips cpu_data[];