Commit 714d8e7e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "Here are the core arm64 updates for 4.1.

  Highlights include a significant rework to head.S (allowing us to boot
  on machines with physical memory at a really high address), an AES
  performance boost on Cortex-A57 and the ability to run a 32-bit
  userspace with 64k pages (although this requires said userspace to be
  built with a recent binutils).

  The head.S rework spilt over into KVM, so there are some changes under
  arch/arm/ which have been acked by Marc Zyngier (KVM co-maintainer).
  In particular, the linker script changes caused us some issues in
  -next, so there are a few merge commits where we had to apply fixes on
  top of a stable branch.

  Other changes include:

   - AES performance boost for Cortex-A57
   - AArch32 (compat) userspace with 64k pages
   - Cortex-A53 erratum workaround for #845719
   - defconfig updates (new platforms, PCI, ...)"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (39 commits)
  arm64: fix midr range for Cortex-A57 erratum 832075
  arm64: errata: add workaround for cortex-a53 erratum #845719
  arm64: Use bool function return values of true/false not 1/0
  arm64: defconfig: updates for 4.1
  arm64: Extract feature parsing code from cpu_errata.c
  arm64: alternative: Allow immediate branch as alternative instruction
  arm64: insn: Add aarch64_insn_decode_immediate
  ARM: kvm: round HYP section to page size instead of log2 upper bound
  ARM: kvm: assert on HYP section boundaries not actual code size
  arm64: head.S: ensure idmap_t0sz is visible
  arm64: pmu: add support for interrupt-affinity property
  dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity
  arm64: head.S: ensure visibility of page tables
  arm64: KVM: use ID map with increased VA range if required
  arm64: mm: increase VA range of identity map
  ARM: kvm: implement replacement for ld's LOG2CEIL()
  arm64: proc: remove unused cpu_get_pgd macro
  arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol
  arm64: remove __calc_phys_offset
  arm64: merge __enable_mmu and __turn_mmu_on
  ...
parents d19d5efd 6d1966df

Documentation/devicetree/bindings/arm/pmu.txt

+7 −0
Original line number Diff line number Diff line
@@ -26,6 +26,13 @@ Required properties: 


Optional properties:



- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles

                       to CPU nodes corresponding directly to the affinity of

		       the SPIs listed in the interrupts property.



		       This property should be present when there is more than

		       a single SPI.



- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd

                     events.

arch/arm/include/asm/kvm_mmu.h

+10 −0
Original line number Diff line number Diff line
@@ -269,6 +269,16 @@ static inline void __kvm_flush_dcache_pud(pud_t pud) 
void kvm_set_way_flush(struct kvm_vcpu *vcpu);

void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);



static inline bool __kvm_cpu_uses_extended_idmap(void)

{

	return false;

}



static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,

				       pgd_t *hyp_pgd,

				       pgd_t *merged_hyp_pgd,

				       unsigned long hyp_idmap_start) { }



#endif	/* !__ASSEMBLY__ */



#endif /* __ARM_KVM_MMU_H__ */

arch/arm/kernel/vmlinux.lds.S

+7 −4
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
	VMLINUX_SYMBOL(__idmap_text_start) = .;				\

	*(.idmap.text)							\

	VMLINUX_SYMBOL(__idmap_text_end) = .;				\

	. = ALIGN(32);							\

	. = ALIGN(PAGE_SIZE);						\

	VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;			\

	*(.hyp.idmap.text)						\

	VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
@@ -343,8 +343,11 @@ SECTIONS 
 */

ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")

ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")



/*

 * The HYP init code can't be more than a page long.

 * The HYP init code can't be more than a page long,

 * and should not cross a page boundary.

 * The above comment applies as well.

 */

ASSERT(((__hyp_idmap_text_end - __hyp_idmap_text_start) <= PAGE_SIZE), "HYP init code too big")
 
ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,

	"HYP init code too big or misaligned")

arch/arm/kvm/mmu.c

+30 −39
Original line number Diff line number Diff line
@@ -35,9 +35,9 @@ extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[]; 


static pgd_t *boot_hyp_pgd;

static pgd_t *hyp_pgd;

static pgd_t *merged_hyp_pgd;

static DEFINE_MUTEX(kvm_hyp_pgd_mutex);



static void *init_bounce_page;

static unsigned long hyp_idmap_start;

static unsigned long hyp_idmap_end;

static phys_addr_t hyp_idmap_vector;
@@ -405,9 +405,6 @@ void free_boot_hyp_pgd(void) 
	if (hyp_pgd)

		unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);



	free_page((unsigned long)init_bounce_page);

	init_bounce_page = NULL;



	mutex_unlock(&kvm_hyp_pgd_mutex);

}
@@ -438,6 +435,11 @@ void free_hyp_pgds(void) 
		free_pages((unsigned long)hyp_pgd, hyp_pgd_order);

		hyp_pgd = NULL;

	}

	if (merged_hyp_pgd) {

		clear_page(merged_hyp_pgd);

		free_page((unsigned long)merged_hyp_pgd);

		merged_hyp_pgd = NULL;

	}



	mutex_unlock(&kvm_hyp_pgd_mutex);

}
@@ -1622,11 +1624,17 @@ void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu) 


phys_addr_t kvm_mmu_get_httbr(void)

{

	if (__kvm_cpu_uses_extended_idmap())

		return virt_to_phys(merged_hyp_pgd);

	else

		return virt_to_phys(hyp_pgd);

}



phys_addr_t kvm_mmu_get_boot_httbr(void)

{

	if (__kvm_cpu_uses_extended_idmap())

		return virt_to_phys(merged_hyp_pgd);

	else

		return virt_to_phys(boot_hyp_pgd);

}
@@ -1643,39 +1651,11 @@ int kvm_mmu_init(void) 
	hyp_idmap_end = kvm_virt_to_phys(__hyp_idmap_text_end);

	hyp_idmap_vector = kvm_virt_to_phys(__kvm_hyp_init);



	if ((hyp_idmap_start ^ hyp_idmap_end) & PAGE_MASK) {

	/*

		 * Our init code is crossing a page boundary. Allocate

		 * a bounce page, copy the code over and use that.

	 * We rely on the linker script to ensure at build time that the HYP

	 * init code does not cross a page boundary.

	 */

		size_t len = __hyp_idmap_text_end - __hyp_idmap_text_start;

		phys_addr_t phys_base;



		init_bounce_page = (void *)__get_free_page(GFP_KERNEL);

		if (!init_bounce_page) {

			kvm_err("Couldn't allocate HYP init bounce page\n");

			err = -ENOMEM;

			goto out;

		}



		memcpy(init_bounce_page, __hyp_idmap_text_start, len);

		/*

		 * Warning: the code we just copied to the bounce page

		 * must be flushed to the point of coherency.

		 * Otherwise, the data may be sitting in L2, and HYP

		 * mode won't be able to observe it as it runs with

		 * caches off at that point.

		 */

		kvm_flush_dcache_to_poc(init_bounce_page, len);



		phys_base = kvm_virt_to_phys(init_bounce_page);

		hyp_idmap_vector += phys_base - hyp_idmap_start;

		hyp_idmap_start = phys_base;

		hyp_idmap_end = phys_base + len;



		kvm_info("Using HYP init bounce page @%lx\n",

			 (unsigned long)phys_base);

	}

	BUG_ON((hyp_idmap_start ^ (hyp_idmap_end - 1)) & PAGE_MASK);



	hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, hyp_pgd_order);

	boot_hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, hyp_pgd_order);
@@ -1698,6 +1678,17 @@ int kvm_mmu_init(void) 
		goto out;

	}



	if (__kvm_cpu_uses_extended_idmap()) {

		merged_hyp_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);

		if (!merged_hyp_pgd) {

			kvm_err("Failed to allocate extra HYP pgd\n");

			goto out;

		}

		__kvm_extend_hypmap(boot_hyp_pgd, hyp_pgd, merged_hyp_pgd,

				    hyp_idmap_start);

		return 0;

	}



	/* Map the very same page at the trampoline VA */

	err = 	__create_hyp_mappings(boot_hyp_pgd,

				      TRAMPOLINE_VA, TRAMPOLINE_VA + PAGE_SIZE,

arch/arm64/Kconfig

+32 −3
Original line number Diff line number Diff line
@@ -368,6 +368,27 @@ config ARM64_ERRATUM_832075 


	  If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on COMPAT

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 845719 on Cortex-A53 parts up to r0p4.



	  When running a compat (AArch32) userspace on an affected Cortex-A53

	  part, a load at EL0 from a virtual address that matches the bottom 32

	  bits of the virtual address used by a recent load at (AArch64) EL1

	  might return incorrect data.



	  The workaround is to write the contextidr_el1 register on exception

	  return to a 32-bit task.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



endmenu
@@ -455,8 +476,8 @@ config SCHED_SMT 
	  places. If unsure say N here.



config NR_CPUS

	int "Maximum number of CPUs (2-64)"

	range 2 64

	int "Maximum number of CPUs (2-4096)"

	range 2 4096

	depends on SMP

	# These have to remain sorted largest to smallest

	default "64"
@@ -470,6 +491,10 @@ config HOTPLUG_CPU 


source kernel/Kconfig.preempt



config UP_LATE_INIT

       def_bool y

       depends on !SMP



config HZ

	int

	default 100
@@ -670,7 +695,7 @@ source "fs/Kconfig.binfmt" 


config COMPAT

	bool "Kernel support for 32-bit EL0"

	depends on !ARM64_64K_PAGES

	depends on !ARM64_64K_PAGES || EXPERT

	select COMPAT_BINFMT_ELF

	select HAVE_UID16

	select OLD_SIGSUSPEND3
@@ -681,6 +706,10 @@ config COMPAT 
	  the user helper functions, VFP support and the ptrace interface are

	  handled appropriately by the kernel.



	  If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you

	  will only be able to execute AArch32 binaries that were compiled with

	  64k aligned segments.



	  If you want to execute 32-bit userspace applications, say Y.



config SYSVIPC_COMPAT

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