Commit 713203e3 authored by Atish Patra's avatar Atish Patra Committed by Paul Walmsley
Browse files

RISC-V: Remove per cpu clocksource 



There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.

Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent e21a712a

drivers/clocksource/timer-riscv.c

+2 −4
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void) 
	return get_cycles64();

}



static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {

static struct clocksource riscv_clocksource = {

	.name		= "riscv_clocksource",

	.rating		= 300,

	.mask		= CLOCKSOURCE_MASK(64),
@@ -92,7 +92,6 @@ void riscv_timer_interrupt(void) 
static int __init riscv_timer_init_dt(struct device_node *n)

{

	int cpuid, hartid, error;

	struct clocksource *cs;



	hartid = riscv_of_processor_hartid(n);

	if (hartid < 0) {
@@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) 


	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",

	       __func__, cpuid, hartid);

	cs = per_cpu_ptr(&riscv_clocksource, cpuid);

	error = clocksource_register_hz(cs, riscv_timebase);

	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);

	if (error) {

		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",

		       error, cpuid);

CRA Git | Maintained and supported by SUSTech CRA and CCSE