Commit 712b6aa8 authored by Kuppuswamy Sathyanarayanan's avatar Kuppuswamy Sathyanarayanan Committed by H. Peter Anvin
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intel_mid: Renamed *mrst* to *intel_mid* 



mrst is used as common name to represent all intel_mid type
soc's. But moorsetwon is just one of the intel_mid soc. So
renamed them to use intel_mid.

This patch mainly renames the variables and related
functions that uses *mrst* prefix with *intel_mid*.

To ensure that there are no functional changes, I have compared
the objdump of related files before and after rename and found
the only difference is symbol and name changes.

Signed-off-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: http://lkml.kernel.org/r/1382049336-21316-6-git-send-email-david.a.cohen@linux.intel.com


Signed-off-by: default avatarDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 6c21b176

Documentation/kernel-parameters.txt

+3 −3
Original line number Diff line number Diff line
@@ -3471,11 +3471,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			default x2apic cluster mode on platforms

			supporting x2apic.



	x86_mrst_timer= [X86-32,APBT]

			Choose timer option for x86 Moorestown MID platform.

	x86_intel_mid_timer= [X86-32,APBT]

			Choose timer option for x86 Intel MID platform.

			Two valid options are apbt timer only and lapic timer

			plus one apbt timer for broadcast timer.

			x86_mrst_timer=apbt_only | lapic_and_apbt

			x86_intel_mid_timer=apbt_only | lapic_and_apbt



	xen_emul_unplug=		[HW,X86,XEN]

			Unplug Xen emulated devices

arch/x86/include/asm/intel-mid.h

+13 −13
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 


#include <linux/sfi.h>



extern int pci_mrst_init(void);

extern int intel_mid_pci_init(void);

extern int __init sfi_parse_mrtc(struct sfi_table_header *table);

extern int sfi_mrtc_num;

extern struct sfi_rtc_table_entry sfi_mrtc_array[];
@@ -25,33 +25,33 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 
 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be

 * identified via MSRs.

 */

enum mrst_cpu_type {

enum intel_mid_cpu_type {

	/* 1 was Moorestown */

	MRST_CPU_CHIP_PENWELL = 2,

	INTEL_MID_CPU_CHIP_PENWELL = 2,

};



extern enum mrst_cpu_type __mrst_cpu_chip;

extern enum intel_mid_cpu_type __intel_mid_cpu_chip;



#ifdef CONFIG_X86_INTEL_MID



static inline enum mrst_cpu_type mrst_identify_cpu(void)

static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)

{

	return __mrst_cpu_chip;

	return __intel_mid_cpu_chip;

}



#else /* !CONFIG_X86_INTEL_MID */



#define mrst_identify_cpu()    (0)

#define intel_mid_identify_cpu()    (0)



#endif /* !CONFIG_X86_INTEL_MID */



enum mrst_timer_options {

	MRST_TIMER_DEFAULT,

	MRST_TIMER_APBT_ONLY,

	MRST_TIMER_LAPIC_APBT,

enum intel_mid_timer_options {

	INTEL_MID_TIMER_DEFAULT,

	INTEL_MID_TIMER_APBT_ONLY,

	INTEL_MID_TIMER_LAPIC_APBT,

};



extern enum mrst_timer_options mrst_timer_options;

extern enum intel_mid_timer_options intel_mid_timer_options;



/*

 * Penwell uses spread spectrum clock, so the freq number is not exactly
@@ -76,6 +76,6 @@ extern void intel_scu_devices_destroy(void); 
#define MRST_VRTC_MAP_SZ	(1024)

/*#define MRST_VRTC_PGOFFSET	(0xc00) */



extern void mrst_rtc_init(void);

extern void intel_mid_rtc_init(void);



#endif /* _ASM_X86_INTEL_MID_H */

arch/x86/include/asm/setup.h

+2 −2
Original line number Diff line number Diff line
@@ -51,9 +51,9 @@ extern void i386_reserve_resources(void); 
extern void setup_default_timer_irq(void);



#ifdef CONFIG_X86_INTEL_MID

extern void x86_mrst_early_setup(void);

extern void x86_intel_mid_early_setup(void);

#else

static inline void x86_mrst_early_setup(void) { }

static inline void x86_intel_mid_early_setup(void) { }

#endif



#ifdef CONFIG_X86_INTEL_CE

arch/x86/include/uapi/asm/bootparam.h

+1 −1
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ enum { 
	X86_SUBARCH_PC = 0,

	X86_SUBARCH_LGUEST,

	X86_SUBARCH_XEN,

	X86_SUBARCH_MRST,

	X86_SUBARCH_INTEL_MID,

	X86_SUBARCH_CE4100,

	X86_NR_SUBARCHS,

};

arch/x86/kernel/apb_timer.c

+4 −4
Original line number Diff line number Diff line
@@ -157,13 +157,13 @@ static int __init apbt_clockevent_register(void) 


	adev->num = smp_processor_id();

	adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",

		mrst_timer_options == MRST_TIMER_LAPIC_APBT ?

		intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?

		APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,

		adev_virt_addr(adev), 0, apbt_freq);

	/* Firmware does EOI handling for us. */

	adev->timer->eoi = NULL;



	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {

	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {

		global_clock_event = &adev->timer->ced;

		printk(KERN_DEBUG "%s clockevent registered as global\n",

		       global_clock_event->name);
@@ -253,7 +253,7 @@ static int apbt_cpuhp_notify(struct notifier_block *n, 


static __init int apbt_late_init(void)

{

	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||

	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||

		!apb_timer_block_enabled)

		return 0;

	/* This notifier should be called after workqueue is ready */
@@ -340,7 +340,7 @@ void __init apbt_time_init(void) 
	}

#ifdef CONFIG_SMP

	/* kernel cmdline disable apb timer, so we will use lapic timers */

	if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {

	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {

		printk(KERN_INFO "apbt: disabled per cpu timer\n");

		return;

	}

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