Commit 710e0ced authored by Anthony Koo's avatar Anthony Koo Committed by Alex Deucher
Browse files

drm/amd/display: Update register defines 



[Why]
Some register defines are redundant or updated

[How]
Update register defines
Remove some redundant defines

Signed-off-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: default avatarWyatt Wood <Wyatt.Wood@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarSun peng Li <Sunpeng.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7ba99b43

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h

+0 −20
Original line number Diff line number Diff line
@@ -36,26 +36,6 @@ 
#define BASE(seg) \

	BASE_INNER(seg)



#define SR(reg_name)\

		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \

					mm ## reg_name



#define SRI(reg_name, block, id)\

	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SRI2(reg_name, block, id)\

	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

					mm ## reg_name



#define SRII(reg_name, block, id)\

	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix





#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \

	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h

+0 −7
Original line number Diff line number Diff line
@@ -34,13 +34,6 @@ 
#define BASE(seg) \

	BASE_INNER(seg)



#define SRI(reg_name, block, id)\

	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix



#define DCN20_VMID_REG_LIST(id)\

	SRI(CNTL, DCN_VM_CONTEXT, id),\

	SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\

CRA Git | Maintained and supported by SUSTech CRA and CCSE