Commit 70f0c230 authored by Tony W Wang-oc's avatar Tony W Wang-oc Committed by Borislav Petkov
Browse files

x86/mce: Add Zhaoxin LMCE support 



Newer Zhaoxin CPUs support LMCE compatible with Intel. Add support for
that.

 [ bp: Export functions and massage. ]

Signed-off-by: default avatarTony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-5-git-send-email-TonyWWang-oc@zhaoxin.com
parent 5a3d56a0

arch/x86/kernel/cpu/mce/core.c

+20 −2
Original line number Diff line number Diff line
@@ -1132,6 +1132,12 @@ static bool __mc_check_crashing_cpu(int cpu) 
		u64 mcgstatus;



		mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);



		if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {

			if (mcgstatus & MCG_STATUS_LMCES)

				return false;

		}



		if (mcgstatus & MCG_STATUS_RIPV) {

			mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);

			return true;
@@ -1282,9 +1288,10 @@ void do_machine_check(struct pt_regs *regs, long error_code) 


	/*

	 * Check if this MCE is signaled to only this logical processor,

	 * on Intel only.

	 * on Intel, Zhaoxin only.

	 */

	if (m.cpuvendor == X86_VENDOR_INTEL)

	if (m.cpuvendor == X86_VENDOR_INTEL ||

	    m.cpuvendor == X86_VENDOR_ZHAOXIN)

		lmce = m.mcgstatus & MCG_STATUS_LMCES;



	/*
@@ -1797,9 +1804,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 
	}



	intel_init_cmci();

	intel_init_lmce();

	mce_adjust_timer = cmci_intel_adjust_timer;

}



static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)

{

	intel_clear_lmce();

}



static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)

{

	switch (c->x86_vendor) {
@@ -1836,6 +1849,11 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 
	case X86_VENDOR_INTEL:

		mce_intel_feature_clear(c);

		break;



	case X86_VENDOR_ZHAOXIN:

		mce_zhaoxin_feature_clear(c);

		break;



	default:

		break;

	}

arch/x86/kernel/cpu/mce/intel.c

+2 −2
Original line number Diff line number Diff line
@@ -444,7 +444,7 @@ void intel_init_cmci(void) 
	cmci_recheck();

}



static void intel_init_lmce(void)

void intel_init_lmce(void)

{

	u64 val;
@@ -457,7 +457,7 @@ static void intel_init_lmce(void) 
		wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);

}



static void intel_clear_lmce(void)

void intel_clear_lmce(void)

{

	u64 val;

arch/x86/kernel/cpu/mce/internal.h

+4 −0
Original line number Diff line number Diff line
@@ -46,12 +46,16 @@ bool mce_intel_cmci_poll(void); 
void mce_intel_hcpu_update(unsigned long cpu);

void cmci_disable_bank(int bank);

void intel_init_cmci(void);

void intel_init_lmce(void);

void intel_clear_lmce(void);

#else

# define cmci_intel_adjust_timer mce_adjust_timer_default

static inline bool mce_intel_cmci_poll(void) { return false; }

static inline void mce_intel_hcpu_update(unsigned long cpu) { }

static inline void cmci_disable_bank(int bank) { }

static inline void intel_init_cmci(void) { }

static inline void intel_init_lmce(void) { }

static inline void intel_clear_lmce(void) { }

#endif



void mce_timer_kick(unsigned long interval);

CRA Git | Maintained and supported by SUSTech CRA and CCSE