Commit 70c8b4b8 authored by Hyun Kwon's avatar Hyun Kwon
Browse files

drm: xlnx: zynqmp: Use switch - case for link rate downshift 



Use switch - case to downshift from the current link rate. It's a small
loop now, so fine to be replaced with switch - case. With a loop, it is
confusing and hard to follow as reported below.

The patch d76271d2: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
DisplayPort Subsystem" from Jul 7, 2018, leads to the following
static checker warning:

	drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
	error: iterator underflow 'bws' (-1)-2

Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarHyun Kwon <hyun.kwon@xilinx.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1596065445-4630-1-git-send-email-hyun.kwon@xilinx.com
parent 2d889db7

drivers/gpu/drm/xlnx/zynqmp_dp.c

+16 −13
Original line number Diff line number Diff line
@@ -567,23 +567,26 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, 
				    u8 current_bw)

{

	int max_rate = dp->link_config.max_rate;

	u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };

	u8 bw_code;

	u8 max_lanes = dp->link_config.max_lanes;

	u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);

	u8 bpp = dp->config.bpp;

	u8 lane_cnt;

	s8 i;



	if (current_bw == DP_LINK_BW_1_62) {

	/* Downshift from current bandwidth */

	switch (current_bw) {

	case DP_LINK_BW_5_4:

		bw_code = DP_LINK_BW_2_7;

		break;

	case DP_LINK_BW_2_7:

		bw_code = DP_LINK_BW_1_62;

		break;

	case DP_LINK_BW_1_62:

		dev_err(dp->dev, "can't downshift. already lowest link rate\n");

		return -EINVAL;

	}



	for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {

		if (current_bw && bws[i] >= current_bw)

			continue;



		if (bws[i] <= max_link_rate_code)

	default:

		/* If not given, start with max supported */

		bw_code = max_link_rate_code;

		break;

	}
@@ -591,10 +594,10 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, 
		int bw;

		u32 rate;



		bw = drm_dp_bw_code_to_link_rate(bws[i]);

		bw = drm_dp_bw_code_to_link_rate(bw_code);

		rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);

		if (pclock <= rate) {

			dp->mode.bw_code = bws[i];

			dp->mode.bw_code = bw_code;

			dp->mode.lane_cnt = lane_cnt;

			dp->mode.pclock = pclock;

			return dp->mode.bw_code;

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