Merge tag 'powerpc-4.7-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux (70bd68d7) · Commits · 戴 / test

arch/powerpc/include/asm/book3s/64/pgtable.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -230,6 +230,7 @@ extern unsigned long __kernel_virt_size;
		#define KERN_VIRT_SIZE __kernel_virt_size
		extern struct page *vmemmap;
		extern unsigned long ioremap_bot;
		extern unsigned long pci_io_base;
		#endif /* __ASSEMBLY__ */

		#include <asm/book3s/64/hash.h>

arch/powerpc/kernel/eeh_driver.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -647,7 +647,7 @@ static int eeh_reset_device(struct eeh_pe pe, struct pci_bus bus,
		pci_unlock_rescan_remove();
		}
		} else if (frozen_bus) {
		eeh_pe_dev_traverse(pe, eeh_rmv_device, &rmv_data);
		eeh_pe_dev_traverse(pe, eeh_rmv_device, rmv_data);
		}

		/*

arch/powerpc/kernel/pci_64.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -47,7 +47,6 @@ static int __init pcibios_init(void)

		printk(KERN_INFO "PCI: Probing PCI hardware\n");

		pci_io_base = ISA_IO_BASE;
		/* For now, override phys_mem_access_prot. If we need it,g
		* later, we may move that initialization to each ppc_md
		*/

arch/powerpc/kernel/process.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -1505,6 +1505,16 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
		current->thread.regs = regs - 1;
		}

		#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
		/*
		* Clear any transactional state, we're exec()ing. The cause is
		* not important as there will never be a recheckpoint so it's not
		* user visible.
		*/
		if (MSR_TM_SUSPENDED(mfmsr()))
		tm_reclaim_current(0);
		#endif

		memset(regs->gpr, 0, sizeof(regs->gpr));
		regs->ctr = 0;
		regs->link = 0;

arch/powerpc/kernel/tm.S

+44 −17

Original line number	Diff line number	Diff line
		@@ -110,17 +110,11 @@ _GLOBAL(tm_reclaim)
		std r3, STK_PARAM(R3)(r1)
		SAVE_NVGPRS(r1)

		/* We need to setup MSR for VSX register save instructions. Here we
		* also clear the MSR RI since when we do the treclaim, we won't have a
		* valid kernel pointer for a while. We clear RI here as it avoids
		* adding another mtmsr closer to the treclaim. This makes the region
		* maked as non-recoverable wider than it needs to be but it saves on
		* inserting another mtmsrd later.
		*/
		/* We need to setup MSR for VSX register save instructions. */
		mfmsr r14
		mr r15, r14
		ori r15, r15, MSR_FP
		li r16, MSR_RI
		li r16, 0
		ori r16, r16, MSR_EE /* IRQs hard off */
		andc r15, r15, r16
		oris r15, r15, MSR_VEC@h
		@@ -176,7 +170,17 @@ dont_backup_fp:
		1: tdeqi r6, 0
		EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0

		/* The moment we treclaim, ALL of our GPRs will switch
		/* Clear MSR RI since we are about to change r1, EE is already off. */
		li r4, 0
		mtmsrd r4, 1

		/*
		* BE CAREFUL HERE:
		* At this point we can't take an SLB miss since we have MSR_RI
		* off. Load only to/from the stack/paca which are in SLB bolted regions
		* until we turn MSR RI back on.
		*
		* The moment we treclaim, ALL of our GPRs will switch
		* to user register state. (FPRs, CCR etc. also!)
		* Use an sprg and a tm_scratch in the PACA to shuffle.
		*/
		@@ -197,6 +201,11 @@ dont_backup_fp:

		/* Store the PPR in r11 and reset to decent value */
		std r11, GPR11(r1) /* Temporary stash */

		/* Reset MSR RI so we can take SLB faults again */
		li r11, MSR_RI
		mtmsrd r11, 1

		mfspr r11, SPRN_PPR
		HMT_MEDIUM

		@@ -397,11 +406,6 @@ restore_gprs:
		ld r5, THREAD_TM_DSCR(r3)
		ld r6, THREAD_TM_PPR(r3)

		/* Clear the MSR RI since we are about to change R1. EE is already off
		*/
		li r4, 0
		mtmsrd r4, 1

		REST_GPR(0, r7) /* GPR0 */
		REST_2GPRS(2, r7) /* GPR2-3 */
		REST_GPR(4, r7) /* GPR4 */
		@@ -439,10 +443,33 @@ restore_gprs:
		ld r6, _CCR(r7)
		mtcr r6

		REST_GPR(1, r7) /* GPR1 */
		REST_GPR(5, r7) /* GPR5-7 */
		REST_GPR(6, r7)
		ld r7, GPR7(r7)

		/*
		* Store r1 and r5 on the stack so that we can access them
		* after we clear MSR RI.
		*/

		REST_GPR(5, r7)
		std r5, -8(r1)
		ld r5, GPR1(r7)
		std r5, -16(r1)

		REST_GPR(7, r7)

		/* Clear MSR RI since we are about to change r1. EE is already off */
		li r5, 0
		mtmsrd r5, 1

		/*
		* BE CAREFUL HERE:
		* At this point we can't take an SLB miss since we have MSR_RI
		* off. Load only to/from the stack/paca which are in SLB bolted regions
		* until we turn MSR RI back on.
		*/

		ld r5, -8(r1)
		ld r1, -16(r1)

		/* Commit register state as checkpointed state: */
		TRECHKPT

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