Commit 70ada779 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6 

* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (53 commits)
  spi/omap2_mcspi: Verify TX reg is empty after TX only xfer with DMA
  spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
  spi/bfin_spi: namespace local structs
  spi/bfin_spi: init early
  spi/bfin_spi: check per-transfer bits_per_word
  spi/bfin_spi: warn when CS is driven by hardware (CPHA=0)
  spi/bfin_spi: cs should be always low when a new transfer begins
  spi/bfin_spi: fix typo in comment
  spi/bfin_spi: reject unsupported SPI modes
  spi/bfin_spi: use dma_disable_irq_nosync() in irq handler
  spi/bfin_spi: combine duplicate SPI_CTL read/write logic
  spi/bfin_spi: reset ctl_reg bits when setup is run again on a device
  spi/bfin_spi: push all size checks into the transfer function
  spi/bfin_spi: use nosync when disabling the IRQ from the IRQ handler
  spi/bfin_spi: sync hardware state before reprogramming everything
  spi/bfin_spi: save/restore state when suspending/resuming
  spi/bfin_spi: redo GPIO CS handling
  Blackfin: SPI: expand SPI bitmasks
  spi/bfin_spi: use the SPI namespaced bit names
  spi/bfin_spi: drop extra memory we don't need
  ...
parents b22793f7 2764c500

Documentation/powerpc/dts-bindings/fsl/spi.txt

+23 −1
Original line number Diff line number Diff line 
* SPI (Serial Peripheral Interface)



Required properties:

- cell-index : SPI controller index.

- cell-index : QE SPI subblock index.

		0: QE subblock SPI1

		1: QE subblock SPI2

- compatible : should be "fsl,spi".

- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".

- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example: 
		gpios = <&gpio 18 1	// device reg=<0>

			 &gpio 19 1>;	// device reg=<1>

	};





* eSPI (Enhanced Serial Peripheral Interface)



Required properties:

- compatible : should be "fsl,mpc8536-espi".

- reg : Offset and length of the register set for the device.

- interrupts : should contain eSPI interrupt, the device has one interrupt.

- fsl,espi-num-chipselects : the number of the chipselect signals.



Example:

	spi@110000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "fsl,mpc8536-espi";

		reg = <0x110000 0x1000>;

		interrupts = <53 0x2>;

		interrupt-parent = <&mpic>;

		fsl,espi-num-chipselects = <4>;

	};

arch/arm/mach-lpc32xx/phy3250.c

+1 −6
Original line number Diff line number Diff line
@@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control) 
}



static struct pl022_config_chip spi0_chip_info = {

	.lbm			= LOOPBACK_DISABLED,

	.com_mode		= INTERRUPT_TRANSFER,

	.iface			= SSP_INTERFACE_MOTOROLA_SPI,

	.hierarchy		= SSP_MASTER,

	.slave_tx_disable	= 0,

	.endian_tx		= SSP_TX_LSB,

	.endian_rx		= SSP_RX_LSB,

	.data_size		= SSP_DATA_BITS_8,

	.rx_lev_trig		= SSP_RX_4_OR_MORE_ELEM,

	.tx_lev_trig		= SSP_TX_4_OR_MORE_EMPTY_LOC,

	.clk_phase		= SSP_CLK_FIRST_EDGE,

	.clk_pol		= SSP_CLK_POL_IDLE_LOW,

	.ctrl_len		= SSP_BITS_8,

	.wait_state		= SSP_MWIRE_WAIT_ZERO,

	.duplex			= SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void) 
			.max_speed_hz = 5000000,

			.bus_num = 0,

			.chip_select = 0,

			.mode = SPI_MODE_0,

			.platform_data = &eeprom,

			.controller_data = &spi0_chip_info,

		},

arch/arm/mach-u300/dummyspichip.c

+2 −3
Original line number Diff line number Diff line
@@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev, 
	 * struct, this is just used here to alter the behaviour of the chip

	 * in order to perform tests.

	 */

	struct pl022_config_chip *chip_info = spi->controller_data;

	int status;

	u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD,

			0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05,
@@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev, 
	 * Force chip to 8 bit mode

	 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!

	 */

	chip_info->data_size = SSP_DATA_BITS_8;

	spi->bits_per_word = 8;

	/* You should NOT DO THIS EITHER */

	spi->master->setup(spi);
@@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev, 
	 * Force chip to 16 bit mode

	 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!

	 */

	chip_info->data_size = SSP_DATA_BITS_16;

	spi->bits_per_word = 16;

	/* You should NOT DO THIS EITHER */

	spi->master->setup(spi);

arch/arm/mach-u300/spi.c

+1 −9
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect) 
}



struct pl022_config_chip dummy_chip_info = {

	/* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */

	.lbm = LOOPBACK_ENABLED,

	/*

	 * available POLLING_TRANSFER and INTERRUPT_TRANSFER,

	 * DMA_TRANSFER does not work
@@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = { 
	.hierarchy = SSP_MASTER,

	/* 0 = drive TX even as slave, 1 = do not drive TX as slave */

	.slave_tx_disable = 0,

	/* LSB first */

	.endian_tx = SSP_TX_LSB,

	.endian_rx = SSP_RX_LSB,

	.data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */

	.rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,

	.tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,

	.clk_phase = SSP_CLK_SECOND_EDGE,

	.clk_pol = SSP_CLK_POL_IDLE_LOW,

	.ctrl_len = SSP_BITS_12,

	.wait_state = SSP_MWIRE_WAIT_ZERO,

	.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = { 
		.bus_num        = 0, /* Only one bus on this chip */

		.chip_select    = 0,

		/* Means SPI_CS_HIGH, change if e.g low CS */

		.mode           = 0,

		.mode           = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,

	},

#endif

};

arch/arm/mach-ux500/board-mop500.c

+1 −7
Original line number Diff line number Diff line
@@ -55,19 +55,13 @@ static void ab4500_spi_cs_control(u32 command) 
}



struct pl022_config_chip ab4500_chip_info = {

	.lbm = LOOPBACK_DISABLED,

	.com_mode = INTERRUPT_TRANSFER,

	.iface = SSP_INTERFACE_MOTOROLA_SPI,

	/* we can act as master only */

	.hierarchy = SSP_MASTER,

	.slave_tx_disable = 0,

	.endian_rx = SSP_RX_MSB,

	.endian_tx = SSP_TX_MSB,

	.data_size = SSP_DATA_BITS_24,

	.rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,

	.tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,

	.clk_phase = SSP_CLK_SECOND_EDGE,

	.clk_pol = SSP_CLK_POL_IDLE_HIGH,

	.cs_control = ab4500_spi_cs_control,

};
@@ -83,7 +77,7 @@ static struct spi_board_info u8500_spi_devices[] = { 
		.max_speed_hz = 12000000,

		.bus_num = 0,

		.chip_select = 0,

		.mode = SPI_MODE_0,

		.mode = SPI_MODE_3,

		.irq = IRQ_DB8500_AB8500,

	},

};

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