Commit 70a7274a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-5.4-2' of... 

Merge tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.4, 2nd round:
 - Get SNVS power key back to work for imx6-logicpd board. It was
   accidentally disabled by commit 770856f0 ("ARM: dts: imx6qdl:
   Enable SNVS power key according to board design").
 - Fix sparse warnings in IMX GPC driver by making the initializers
   in imx_gpc_domains C99 format.
 - Fix an interrupt storm coming from accelerometer on imx6qdl-sabreauto
   board. This is seen with upstream version U-Boot where pinctrl is not
   configured for the device.
 - Fix sdma device compatible string for i.MX8MM and i.MX8MN SoC.
 - Fix compatible of PCA9547 i2c-mux on LS1028A QDS board to get the
   device probed correctly.

* tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8mn: fix compatible string for sdma
  arm64: dts: imx8mm: fix compatible string for sdma
  ARM: dts: imx6-logicpd: Re-enable SNVS power key
  soc: imx: gpc: fix initialiser format
  ARM: dts: imx6qdl-sabreauto: Fix storm of accelerometer interrupts
  arm64: dts: ls1028a: fix a compatible issue

Link: https://lore.kernel.org/r/20191029110334.GA20928@dragon


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b25e2972 958c6014

arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -328,6 +328,10 @@ 
	pinctrl-0 = <&pinctrl_pwm3>;

};



&snvs_pwrkey {

	status = "okay";

};



&ssi2 {

	status = "okay";

};

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -230,6 +230,8 @@ 
			accelerometer@1c {

				compatible = "fsl,mma8451";

				reg = <0x1c>;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_mma8451_int>;

				interrupt-parent = <&gpio6>;

				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;

			};
@@ -628,6 +630,12 @@ 
			>;

		};



		pinctrl_mma8451_int: mma8451intgrp {

			fsl,pins = <

				MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0xb0b1

			>;

		};



		pinctrl_pwm3: pwm1grp {

			fsl,pins = <

				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1

arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ 
	status = "okay";



	i2c-mux@77 {

		compatible = "nxp,pca9847";

		compatible = "nxp,pca9547";

		reg = <0x77>;

		#address-cells = <1>;

		#size-cells = <0>;

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ 
			};



			sdma2: dma-controller@302c0000 {

				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";

				reg = <0x302c0000 0x10000>;

				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
@@ -405,7 +405,7 @@ 
			};



			sdma3: dma-controller@302b0000 {

				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";

				reg = <0x302b0000 0x10000>;

				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
@@ -737,7 +737,7 @@ 
			};



			sdma1: dma-controller@30bd0000 {

				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";

				reg = <0x30bd0000 0x10000>;

				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -288,7 +288,7 @@ 
			};



			sdma3: dma-controller@302b0000 {

				compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";

				reg = <0x302b0000 0x10000>;

				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
@@ -299,7 +299,7 @@ 
			};



			sdma2: dma-controller@302c0000 {

				compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";

				reg = <0x302c0000 0x10000>;

				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
@@ -612,7 +612,7 @@ 
			};



			sdma1: dma-controller@30bd0000 {

				compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";

				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";

				reg = <0x30bd0000 0x10000>;

				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,

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