irqchip/gic-v3: Describe the SGI range (70a29c32) · Commits · 戴 / test

drivers/irqchip/irq-gic-v3.c

+15 −3

Original line number	Diff line number	Diff line
		@@ -112,6 +112,7 @@ static DEFINE_PER_CPU(bool, has_rss);
		#define DEFAULT_PMR_VALUE 0xf0

		enum gic_intid_range {
		SGI_RANGE,
		PPI_RANGE,
		SPI_RANGE,
		EPPI_RANGE,
		@@ -123,6 +124,8 @@ enum gic_intid_range {
		static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
		{
		switch (hwirq) {
		case 0 ... 15:
		return SGI_RANGE;
		case 16 ... 31:
		return PPI_RANGE;
		case 32 ... 1019:
		@@ -148,15 +151,22 @@ static inline unsigned int gic_irq(struct irq_data *d)
		return d->hwirq;
		}

		static inline int gic_irq_in_rdist(struct irq_data *d)
		static inline bool gic_irq_in_rdist(struct irq_data *d)
		{
		enum gic_intid_range range = get_intid_range(d);
		return range == PPI_RANGE \|\| range == EPPI_RANGE;
		switch (get_intid_range(d)) {
		case SGI_RANGE:
		case PPI_RANGE:
		case EPPI_RANGE:
		return true;
		default:
		return false;
		}
		}

		static inline void __iomem gic_dist_base(struct irq_data d)
		{
		switch (get_intid_range(d)) {
		case SGI_RANGE:
		case PPI_RANGE:
		case EPPI_RANGE:
		/* SGI+PPI -> SGI_base for this CPU */
		@@ -253,6 +263,7 @@ static void gic_enable_redist(bool enable)
		static u32 convert_offset_index(struct irq_data d, u32 offset, u32 index)
		{
		switch (get_intid_range(d)) {
		case SGI_RANGE:
		case PPI_RANGE:
		case SPI_RANGE:
		*index = d->hwirq;
		@@ -1277,6 +1288,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
		chip = &gic_eoimode1_chip;

		switch (__get_intid_range(hw)) {
		case SGI_RANGE:
		case PPI_RANGE:
		case EPPI_RANGE:
		irq_set_percpu_devid(irq);