Commit 709cf19c authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Use patch_site for perf counters setup 



The 8xx TLB miss routines are patched when (de)activating
perf counters.

This patch uses the new patch_site functionality in order
to get a better code readability and avoid a label mess when
dumping the code with 'objdump -d'

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 1a210878

arch/powerpc/include/asm/mmu-8xx.h

+4 −0
Original line number Diff line number Diff line
@@ -234,6 +234,10 @@ extern s32 patch__itlbmiss_linmem_top; 
extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;

extern s32 patch__fixupdar_linmem_top;



extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2;

extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3;

extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;



#endif /* !__ASSEMBLY__ */



#if defined(CONFIG_PPC_4K_PAGES)

arch/powerpc/kernel/head_8xx.S

+19 −14
Original line number Diff line number Diff line
@@ -374,16 +374,17 @@ InstructionTLBMiss: 
	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */



	/* Restore registers */

_ENTRY(itlb_miss_exit_1)

	mfspr	r10, SPRN_SPRG_SCRATCH0

0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

	mfspr	r12, SPRN_SPRG_SCRATCH2

#endif

	rfi

	patch_site	0b, patch__itlbmiss_exit_1



#ifdef CONFIG_PERF_EVENTS

_ENTRY(itlb_miss_perf)

	lis	r10, (itlb_miss_counter - PAGE_OFFSET)@ha

	patch_site	0f, patch__itlbmiss_perf

0:	lis	r10, (itlb_miss_counter - PAGE_OFFSET)@ha

	lwz	r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)

	addi	r11, r11, 1

	stw	r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
@@ -499,14 +500,16 @@ DataStoreTLBMiss: 


	/* Restore registers */

	mtspr	SPRN_DAR, r11	/* Tag DAR */

_ENTRY(dtlb_miss_exit_1)

	mfspr	r10, SPRN_SPRG_SCRATCH0



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r12, SPRN_SPRG_SCRATCH2

	rfi

	patch_site	0b, patch__dtlbmiss_exit_1



#ifdef CONFIG_PERF_EVENTS

_ENTRY(dtlb_miss_perf)

	lis	r10, (dtlb_miss_counter - PAGE_OFFSET)@ha

	patch_site	0f, patch__dtlbmiss_perf

0:	lis	r10, (dtlb_miss_counter - PAGE_OFFSET)@ha

	lwz	r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)

	addi	r11, r11, 1

	stw	r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
@@ -658,11 +661,12 @@ DTLBMissIMMR: 


	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */

_ENTRY(dtlb_miss_exit_2)

	mfspr	r10, SPRN_SPRG_SCRATCH0



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r12, SPRN_SPRG_SCRATCH2

	rfi

	patch_site	0b, patch__dtlbmiss_exit_2



DTLBMissLinear:

	mtcr	r12
@@ -676,11 +680,12 @@ DTLBMissLinear: 


	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */

_ENTRY(dtlb_miss_exit_3)

	mfspr	r10, SPRN_SPRG_SCRATCH0



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r12, SPRN_SPRG_SCRATCH2

	rfi

	patch_site	0b, patch__dtlbmiss_exit_3



#ifndef CONFIG_PIN_TLB_TEXT

ITLBMissLinear:
@@ -693,11 +698,11 @@ ITLBMissLinear: 
			  _PAGE_PRESENT

	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */



_ENTRY(itlb_miss_exit_2)

	mfspr	r10, SPRN_SPRG_SCRATCH0

0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r12, SPRN_SPRG_SCRATCH2

	rfi

	patch_site	0b, patch__itlbmiss_exit_2

#endif



/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions

arch/powerpc/perf/8xx-pmu.c

+12 −15
Original line number Diff line number Diff line
@@ -31,9 +31,6 @@ 


extern unsigned long itlb_miss_counter, dtlb_miss_counter;

extern atomic_t instruction_counter;

extern unsigned int itlb_miss_perf, dtlb_miss_perf;

extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2;

extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3;



static atomic_t insn_ctr_ref;

static atomic_t itlb_miss_ref;
@@ -103,22 +100,22 @@ static int mpc8xx_pmu_add(struct perf_event *event, int flags) 
		break;

	case PERF_8xx_ID_ITLB_LOAD_MISS:

		if (atomic_inc_return(&itlb_miss_ref) == 1) {

			unsigned long target = (unsigned long)&itlb_miss_perf;

			unsigned long target = patch_site_addr(&patch__itlbmiss_perf);



			patch_branch(&itlb_miss_exit_1, target, 0);

			patch_branch_site(&patch__itlbmiss_exit_1, target, 0);

#ifndef CONFIG_PIN_TLB_TEXT

			patch_branch(&itlb_miss_exit_2, target, 0);

			patch_branch_site(&patch__itlbmiss_exit_2, target, 0);

#endif

		}

		val = itlb_miss_counter;

		break;

	case PERF_8xx_ID_DTLB_LOAD_MISS:

		if (atomic_inc_return(&dtlb_miss_ref) == 1) {

			unsigned long target = (unsigned long)&dtlb_miss_perf;

			unsigned long target = patch_site_addr(&patch__dtlbmiss_perf);



			patch_branch(&dtlb_miss_exit_1, target, 0);

			patch_branch(&dtlb_miss_exit_2, target, 0);

			patch_branch(&dtlb_miss_exit_3, target, 0);

			patch_branch_site(&patch__dtlbmiss_exit_1, target, 0);

			patch_branch_site(&patch__dtlbmiss_exit_2, target, 0);

			patch_branch_site(&patch__dtlbmiss_exit_3, target, 0);

		}

		val = dtlb_miss_counter;

		break;
@@ -180,17 +177,17 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) 
		break;

	case PERF_8xx_ID_ITLB_LOAD_MISS:

		if (atomic_dec_return(&itlb_miss_ref) == 0) {

			patch_instruction(&itlb_miss_exit_1, insn);

			patch_instruction_site(&patch__itlbmiss_exit_1, insn);

#ifndef CONFIG_PIN_TLB_TEXT

			patch_instruction(&itlb_miss_exit_2, insn);

			patch_instruction_site(&patch__itlbmiss_exit_2, insn);

#endif

		}

		break;

	case PERF_8xx_ID_DTLB_LOAD_MISS:

		if (atomic_dec_return(&dtlb_miss_ref) == 0) {

			patch_instruction(&dtlb_miss_exit_1, insn);

			patch_instruction(&dtlb_miss_exit_2, insn);

			patch_instruction(&dtlb_miss_exit_3, insn);

			patch_instruction_site(&patch__dtlbmiss_exit_1, insn);

			patch_instruction_site(&patch__dtlbmiss_exit_2, insn);

			patch_instruction_site(&patch__dtlbmiss_exit_3, insn);

		}

		break;

	}

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