Commit 707ecec1 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge tag 'amd-thresholding-fixes-for-3.6' of... 

Merge tag 'amd-thresholding-fixes-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

 into x86/mce

Pull in AMD MCE thresholding fixes for v3.6, from Borislav Petkov:

" Those are a bunch of patches which give the MCE thresholding code a
  hard look and a scrubbing to remove a couple of annoyances like sysfs
  warnings when running CPU off-/online tests and the threshold_bank4 node
  under /sys/devices/system/machinecheck/ is a symlink.

  It also gives proper names to the thresholding banks instead of simply
  enumerating them, like this:

     /sys/devices/system/machinecheck/machinecheck0/
     |-- bank0
     |-- bank1
     |-- bank2
     |-- bank3
     |-- bank4
     |-- bank5
     |-- bank6
     |-- check_interval
     |-- cmci_disabled
     |-- combined_unit
     |   |-- combined_unit
     |       |-- error_count
     |       |-- threshold_limit
     |-- dont_log_ce
     |-- execution_unit
     |   |-- execution_unit
     |       |-- error_count
     |       |-- threshold_limit
     |-- ignore_ce
     |-- insn_fetch
     |   |-- insn_fetch
     |       |-- error_count
     |       |-- threshold_limit
     |-- load_store
     |   |-- load_store
     |       |-- error_count
     |       |-- threshold_limit
     |-- monarch_timeout
     |-- northbridge
     |   |-- dram
     |   |   |-- error_count
     |   |   |-- interrupt_enable
     |   |   |-- threshold_limit
     |   |-- ht_links
     |   |   |-- error_count
     |   |   |-- interrupt_enable
     |   |   |-- threshold_limit
     |   |-- l3_cache
     |       |-- error_count
     |       |-- interrupt_enable
     |       |-- threshold_limit
    ...

  It is tested on all our families >= K8."

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 48d212a2 11122570

arch/x86/include/asm/amd_nb.h

+21 −0
Original line number Diff line number Diff line
@@ -26,10 +26,31 @@ struct amd_l3_cache { 
	u8	 subcaches[4];

};



struct threshold_block {

	unsigned int		block;

	unsigned int		bank;

	unsigned int		cpu;

	u32			address;

	u16			interrupt_enable;

	bool			interrupt_capable;

	u16			threshold_limit;

	struct kobject		kobj;

	struct list_head	miscj;

};



struct threshold_bank {

	struct kobject		*kobj;

	struct threshold_block	*blocks;



	/* initialized to the number of CPUs on the node sharing this bank */

	atomic_t		cpus;

};



struct amd_northbridge {

	struct pci_dev *misc;

	struct pci_dev *link;

	struct amd_l3_cache l3_cache;

	struct threshold_bank *bank4;

};



struct amd_northbridge_info {

arch/x86/kernel/amd_nb.c

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },

	{}

};

EXPORT_SYMBOL(amd_nb_misc_ids);

arch/x86/kernel/cpu/mcheck/mce_amd.c

+123 −141
Original line number Diff line number Diff line 
/*

 *  (c) 2005, 2006 Advanced Micro Devices, Inc.

 *  (c) 2005-2012 Advanced Micro Devices, Inc.

 *  Your use of this code is subject to the terms and conditions of the

 *  GNU general public license version 2. See "COPYING" or

 *  http://www.gnu.org/licenses/gpl.html

 *

 *  Written by Jacob Shin - AMD, Inc.

 *

 *  Support : jacob.shin@amd.com

 *  Support: borislav.petkov@amd.com

 *

 *  April 2006

 *     - added support for AMD Family 0x10 processors

 *  May 2012

 *     - major scrubbing

 *

 *  All MC4_MISCi registers are shared between multi-cores

 */
@@ -25,6 +27,7 @@ 
#include <linux/cpu.h>

#include <linux/smp.h>



#include <asm/amd_nb.h>

#include <asm/apic.h>

#include <asm/idle.h>

#include <asm/mce.h>
@@ -45,23 +48,15 @@ 
#define MASK_BLKPTR_LO    0xFF000000

#define MCG_XBLK_ADDR     0xC0000400



struct threshold_block {

	unsigned int		block;

	unsigned int		bank;

	unsigned int		cpu;

	u32			address;

	u16			interrupt_enable;

	bool			interrupt_capable;

	u16			threshold_limit;

	struct kobject		kobj;

	struct list_head	miscj;

static const char * const th_names[] = {

	"load_store",

	"insn_fetch",

	"combined_unit",

	"",

	"northbridge",

	"execution_unit",

};



struct threshold_bank {

	struct kobject		*kobj;

	struct threshold_block	*blocks;

	cpumask_var_t		cpus;

};

static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);



static unsigned char shared_bank[NR_BANKS] = {
@@ -84,6 +79,26 @@ struct thresh_restart { 
	u16			old_limit;

};



static const char * const bank4_names(struct threshold_block *b)

{

	switch (b->address) {

	/* MSR4_MISC0 */

	case 0x00000413:

		return "dram";



	case 0xc0000408:

		return "ht_links";



	case 0xc0000409:

		return "l3_cache";



	default:

		WARN(1, "Funny MSR: 0x%08x\n", b->address);

		return "";

	}

};





static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)

{

	/*
@@ -224,8 +239,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) 


			if (!block)

				per_cpu(bank_map, cpu) |= (1 << bank);

			if (shared_bank[bank] && c->cpu_core_id)

				break;



			memset(&b, 0, sizeof(b));

			b.cpu			= cpu;
@@ -326,7 +339,7 @@ struct threshold_attr { 
#define SHOW_FIELDS(name)						\

static ssize_t show_ ## name(struct threshold_block *b, char *buf)	\

{									\

	return sprintf(buf, "%lx\n", (unsigned long) b->name);		\

	return sprintf(buf, "%lu\n", (unsigned long) b->name);		\

}

SHOW_FIELDS(interrupt_enable)

SHOW_FIELDS(threshold_limit)
@@ -377,38 +390,21 @@ store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 
	return size;

}



struct threshold_block_cross_cpu {

	struct threshold_block	*tb;

	long			retval;

};



static void local_error_count_handler(void *_tbcc)

{

	struct threshold_block_cross_cpu *tbcc = _tbcc;

	struct threshold_block *b = tbcc->tb;

	u32 low, high;



	rdmsr(b->address, low, high);

	tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);

}



static ssize_t show_error_count(struct threshold_block *b, char *buf)

{

	struct threshold_block_cross_cpu tbcc = { .tb = b, };



	smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);

	return sprintf(buf, "%lx\n", tbcc.retval);

}

	u32 lo, hi;



static ssize_t store_error_count(struct threshold_block *b,

				 const char *buf, size_t count)

{

	struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };

	rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);



	smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);

	return 1;

	return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -

				     (THRESHOLD_MAX - b->threshold_limit)));

}



static struct threshold_attr error_count = {

	.attr = {.name = __stringify(error_count), .mode = 0444 },

	.show = show_error_count,

};



#define RW_ATTR(val)							\

static struct threshold_attr val = {					\

	.attr	= {.name = __stringify(val), .mode = 0644 },		\
@@ -418,7 +414,6 @@ static struct threshold_attr val = { \ 


RW_ATTR(interrupt_enable);

RW_ATTR(threshold_limit);

RW_ATTR(error_count);



static struct attribute *default_attrs[] = {

	&threshold_limit.attr,
@@ -517,7 +512,7 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu, 


	err = kobject_init_and_add(&b->kobj, &threshold_ktype,

				   per_cpu(threshold_banks, cpu)[bank]->kobj,

				   "misc%i", block);

				   (bank == 4 ? bank4_names(b) : th_names[bank]));

	if (err)

		goto out_free;

recurse:
@@ -548,97 +543,90 @@ out_free: 
	return err;

}



static __cpuinit long

local_allocate_threshold_blocks(int cpu, unsigned int bank)

static __cpuinit int __threshold_add_blocks(struct threshold_bank *b)

{

	return allocate_threshold_blocks(cpu, bank, 0,

					 MSR_IA32_MC0_MISC + bank * 4);

}

	struct list_head *head = &b->blocks->miscj;

	struct threshold_block *pos = NULL;

	struct threshold_block *tmp = NULL;

	int err = 0;



/* symlinks sibling shared banks to first core.  first core owns dir/files. */

static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)

{

	int i, err = 0;

	struct threshold_bank *b = NULL;

	struct device *dev = per_cpu(mce_device, cpu);

	char name[32];

	err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);

	if (err)

		return err;



	sprintf(name, "threshold_bank%i", bank);

	list_for_each_entry_safe(pos, tmp, head, miscj) {



#ifdef CONFIG_SMP

	if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {	/* symlink */

		i = cpumask_first(cpu_llc_shared_mask(cpu));

		err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);

		if (err) {

			list_for_each_entry_safe_reverse(pos, tmp, head, miscj)

				kobject_del(&pos->kobj);



		/* first core not up yet */

		if (cpu_data(i).cpu_core_id)

			goto out;

			return err;

		}

	}

	return err;

}



		/* already linked */

		if (per_cpu(threshold_banks, cpu)[bank])

			goto out;

static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)

{

	struct device *dev = per_cpu(mce_device, cpu);

	struct amd_northbridge *nb = NULL;

	struct threshold_bank *b = NULL;

	const char *name = th_names[bank];

	int err = 0;



		b = per_cpu(threshold_banks, i)[bank];

	if (shared_bank[bank]) {



		if (!b)

			goto out;

		nb = node_to_amd_nb(amd_get_nb_id(cpu));

		WARN_ON(!nb);



		err = sysfs_create_link(&dev->kobj, b->kobj, name);

		/* threshold descriptor already initialized on this node? */

		if (nb->bank4) {

			/* yes, use it */

			b = nb->bank4;

			err = kobject_add(b->kobj, &dev->kobj, name);

			if (err)

				goto out;



		cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));

			per_cpu(threshold_banks, cpu)[bank] = b;

			atomic_inc(&b->cpus);



			err = __threshold_add_blocks(b);



			goto out;

		}

#endif

	}



	b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);

	if (!b) {

		err = -ENOMEM;

		goto out;

	}

	if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {

		kfree(b);

		err = -ENOMEM;

		goto out;

	}



	b->kobj = kobject_create_and_add(name, &dev->kobj);

	if (!b->kobj)

	if (!b->kobj) {

		err = -EINVAL;

		goto out_free;



#ifndef CONFIG_SMP

	cpumask_setall(b->cpus);

#else

	cpumask_set_cpu(cpu, b->cpus);

#endif

	}



	per_cpu(threshold_banks, cpu)[bank] = b;



	err = local_allocate_threshold_blocks(cpu, bank);

	if (err)

		goto out_free;

	if (shared_bank[bank]) {

		atomic_set(&b->cpus, 1);



	for_each_cpu(i, b->cpus) {

		if (i == cpu)

			continue;



		dev = per_cpu(mce_device, i);

		if (dev)

			err = sysfs_create_link(&dev->kobj,b->kobj, name);

		if (err)

			goto out;



		per_cpu(threshold_banks, i)[bank] = b;

		/* nb is already initialized, see above */

		WARN_ON(nb->bank4);

		nb->bank4 = b;

	}



	err = allocate_threshold_blocks(cpu, bank, 0,

					MSR_IA32_MC0_MISC + bank * 4);

	if (!err)

		goto out;



 out_free:

	per_cpu(threshold_banks, cpu)[bank] = NULL;

	free_cpumask_var(b->cpus);

	kfree(b);



 out:

	return err;

}
@@ -660,12 +648,6 @@ static __cpuinit int threshold_create_device(unsigned int cpu) 
	return err;

}



/*

 * let's be hotplug friendly.

 * in case of multiple core processors, the first core always takes ownership

 *   of shared sysfs dir/files, and rest of the cores will be symlinked to it.

 */



static void deallocate_threshold_block(unsigned int cpu,

						 unsigned int bank)

{
@@ -686,41 +668,42 @@ static void deallocate_threshold_block(unsigned int cpu, 
	per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;

}



static void __threshold_remove_blocks(struct threshold_bank *b)

{

	struct threshold_block *pos = NULL;

	struct threshold_block *tmp = NULL;



	kobject_del(b->kobj);



	list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)

		kobject_del(&pos->kobj);

}



static void threshold_remove_bank(unsigned int cpu, int bank)

{

	struct amd_northbridge *nb;

	struct threshold_bank *b;

	struct device *dev;

	char name[32];

	int i = 0;



	b = per_cpu(threshold_banks, cpu)[bank];

	if (!b)

		return;



	if (!b->blocks)

		goto free_out;



	sprintf(name, "threshold_bank%i", bank);



#ifdef CONFIG_SMP

	/* sibling symlink */

	if (shared_bank[bank] && b->blocks->cpu != cpu) {

		dev = per_cpu(mce_device, cpu);

		sysfs_remove_link(&dev->kobj, name);

	if (shared_bank[bank]) {

		if (!atomic_dec_and_test(&b->cpus)) {

			__threshold_remove_blocks(b);

			per_cpu(threshold_banks, cpu)[bank] = NULL;



			return;

		} else {

			/*

			 * the last CPU on this node using the shared bank is

			 * going away, remove that bank now.

			 */

			nb = node_to_amd_nb(amd_get_nb_id(cpu));

			nb->bank4 = NULL;

		}

#endif



	/* remove all sibling symlinks before unregistering */

	for_each_cpu(i, b->cpus) {

		if (i == cpu)

			continue;



		dev = per_cpu(mce_device, i);

		if (dev)

			sysfs_remove_link(&dev->kobj, name);

		per_cpu(threshold_banks, i)[bank] = NULL;

	}



	deallocate_threshold_block(cpu, bank);
@@ -728,7 +711,6 @@ static void threshold_remove_bank(unsigned int cpu, int bank) 
free_out:

	kobject_del(b->kobj);

	kobject_put(b->kobj);

	free_cpumask_var(b->cpus);

	kfree(b);

	per_cpu(threshold_banks, cpu)[bank] = NULL;

}

drivers/hwmon/k10temp.c

+1 −4
Original line number Diff line number Diff line
@@ -33,9 +33,6 @@ static bool force; 
module_param(force, bool, 0444);

MODULE_PARM_DESC(force, "force loading on processors with erratum 319");



/* PCI-IDs for Northbridge devices not used anywhere else */

#define PCI_DEVICE_ID_AMD_15H_M10H_NB_F3	0x1403



/* CPUID function 0x80000001, ebx */

#define CPUID_PKGTYPE_MASK	0xf0000000

#define CPUID_PKGTYPE_F		0x00000000
@@ -213,7 +210,7 @@ static DEFINE_PCI_DEVICE_TABLE(k10temp_id_table) = { 
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_NB_F3) },

	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },

	{}

};

MODULE_DEVICE_TABLE(pci, k10temp_id_table);

include/linux/pci_ids.h

+1 −0
Original line number Diff line number Diff line
@@ -517,6 +517,7 @@ 
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM	0x1302

#define PCI_DEVICE_ID_AMD_11H_NB_MISC	0x1303

#define PCI_DEVICE_ID_AMD_11H_NB_LINK	0x1304

#define PCI_DEVICE_ID_AMD_15H_M10H_F3	0x1403

#define PCI_DEVICE_ID_AMD_15H_NB_F0	0x1600

#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601

#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602

CRA Git | Maintained and supported by SUSTech CRA and CCSE