Commit 707502f3 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: ni_stc.h: tidy up Joint_Reset_Register and bits 



Rename the CamelCase. Use the BIT() macro to define the bits.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 72bca4f5

drivers/staging/comedi/drivers/ni_mio_common.c

+12 −14
Original line number Diff line number Diff line
@@ -365,7 +365,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = { 
	[NISTC_G0_AUTOINC_REG]		= { 0x188, 2 },

	[NISTC_G1_AUTOINC_REG]		= { 0x18a, 2 },

	[NISTC_AO_MODE3_REG]		= { 0x18c, 2 },

	[Joint_Reset_Register]		= { 0x190, 2 },

	[NISTC_RESET_REG]		= { 0x190, 2 },

	[Interrupt_A_Enable_Register]	= { 0x192, 2 },

	[Second_IRQ_A_Enable_Register]	= { 0, 0 }, /* E-Series only */

	[Interrupt_B_Enable_Register]	= { 0x196, 2 },
@@ -1612,8 +1612,8 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) 


	ni_release_ai_mite_channel(dev);

	/* ai configuration */

	ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,

		      Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,

		      NISTC_RESET_REG);



	ni_set_bits(dev, Interrupt_A_Enable_Register,

		    AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
@@ -1678,7 +1678,7 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) 
	/* clear interrupts */

	ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);



	ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);



	return 0;

}
@@ -2259,7 +2259,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);



	/* start configuration */

	ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);



	/* disable analog triggering for now, since it

	 * interferes with the use of pfi0 */
@@ -2484,7 +2484,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	}



	/* end configuration */

	ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);



	switch (cmd->scan_begin_src) {

	case TRIG_TIMER:
@@ -2909,7 +2909,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
		return -EIO;

	}



	ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);



	ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
@@ -3092,7 +3092,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	/*  enable sending of ao dma requests */

	ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);



	ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);



	if (cmd->stop_src == TRIG_COUNT) {

		ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
@@ -3195,7 +3195,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 


	ni_release_ao_mite_channel(dev);



	ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);

	ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);

	ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);

	ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
@@ -3229,7 +3229,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 
		ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);

		ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);

	}

	ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);

	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);



	return 0;

}
@@ -3733,7 +3733,7 @@ static const struct mio_regmap ni_gpct_to_stc_regmap[] = { 
	[NITIO_G0_GATE2]	= { 0x1b4, 2 },	/* M-Series only */

	[NITIO_G1_GATE2]	= { 0x1b6, 2 },	/* M-Series only */

	[NITIO_G01_STATUS]	= { G_Status_Register, 2 },

	[NITIO_G01_RESET]	= { Joint_Reset_Register, 2 },

	[NITIO_G01_RESET]	= { NISTC_RESET_REG, 2 },

	[NITIO_G01_STATUS1]	= { Joint_Status_1_Register, 2 },

	[NITIO_G01_STATUS2]	= { Joint_Status_2_Register, 2 },

	[NITIO_G0_DMA_CFG]	= { 0x1b8, 2 },	/* M-Series only */
@@ -3771,8 +3771,6 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 
{

	struct comedi_device *dev = counter->counter_dev->dev;

	unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);

	/* bits in the join reset register which are relevant to counters */

	static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;

	static const unsigned gpct_interrupt_a_enable_mask =

	    G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;

	static const unsigned gpct_interrupt_b_enable_mask =
@@ -3814,7 +3812,7 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 
				gpct_interrupt_b_enable_mask, bits);

		break;

	case NITIO_G01_RESET:

		BUG_ON(bits & ~gpct_joint_reset_mask);

		BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));

		/* fall-through */

	default:

		ni_stc_writew(dev, bits, stc_register);

drivers/staging/comedi/drivers/ni_stc.h

+11 −11
Original line number Diff line number Diff line
@@ -373,6 +373,17 @@ 
#define NISTC_AO_MODE3_SW_GATE			BIT(1)

#define NISTC_AO_MODE3_LAST_GATE_DISABLE	BIT(0)	/* M-Series only */



#define NISTC_RESET_REG			72

#define NISTC_RESET_SOFTWARE		BIT(11)

#define NISTC_RESET_AO_CFG_END		BIT(9)

#define NISTC_RESET_AI_CFG_END		BIT(8)

#define NISTC_RESET_AO_CFG_START	BIT(5)

#define NISTC_RESET_AI_CFG_START	BIT(4)

#define NISTC_RESET_G1			BIT(3)

#define NISTC_RESET_G0			BIT(2)

#define NISTC_RESET_AO			BIT(1)

#define NISTC_RESET_AI			BIT(0)



#define AI_Status_1_Register		2

#define Interrupt_A_St				0x8000

#define AI_FIFO_Full_St				0x4000
@@ -431,17 +442,6 @@ enum Joint_Status_2_Bits { 
#define AO_BC_Save_Registers		18

#define AO_UC_Save_Registers		20



#define Joint_Reset_Register		72

#define Software_Reset			_bit11

#define AO_Configuration_End			_bit9

#define AI_Configuration_End			_bit8

#define AO_Configuration_Start			_bit5

#define AI_Configuration_Start			_bit4

#define G1_Reset				_bit3

#define G0_Reset				_bit2

#define AO_Reset				_bit1

#define AI_Reset				_bit0



#define Interrupt_A_Enable_Register	73

#define Pass_Thru_0_Interrupt_Enable		_bit9

#define G0_Gate_Interrupt_Enable		_bit8

CRA Git | Maintained and supported by SUSTech CRA and CCSE