Commit 705a2b5b authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to indirect reg access helper 



Switch WREG32/RREG32_PCIE to use indirect reg access
helper for soc15 and onwards

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1bba3683

drivers/gpu/drm/amd/amdgpu/nv.c

+8 −43
Original line number Diff line number Diff line
@@ -69,75 +69,40 @@ static const struct amd_ip_funcs nv_common_ip_funcs; 
 */

static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;

	u32 r;

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, reg);

	(void)RREG32(address);

	r = RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	return r;

	return amdgpu_device_indirect_rreg(adev, address, data, reg);

}



static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long flags, address, data;

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, reg);

	(void)RREG32(address);

	WREG32(data, v);

	(void)RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	amdgpu_device_indirect_wreg(adev, address, data, reg, v);

}



static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;

	u64 r;

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	/* read low 32 bit */

	WREG32(address, reg);

	(void)RREG32(address);

	r = RREG32(data);



	/* read high 32 bit*/

	WREG32(address, reg + 4);

	(void)RREG32(address);

	r |= ((u64)RREG32(data) << 32);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	return r;

	return amdgpu_device_indirect_rreg64(adev, address, data, reg);

}



static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)

{

	unsigned long flags, address, data;

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	/* write low 32 bit */

	WREG32(address, reg);

	(void)RREG32(address);

	WREG32(data, (u32)(v & 0xffffffffULL));

	(void)RREG32(data);



	/* write high 32 bit */

	WREG32(address, reg + 4);

	(void)RREG32(address);

	WREG32(data, (u32)(v >> 32));

	(void)RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);

}



static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)

drivers/gpu/drm/amd/amdgpu/soc15.c

+8 −43
Original line number Diff line number Diff line
@@ -101,75 +101,40 @@ 
 */

static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;

	u32 r;

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, reg);

	(void)RREG32(address);

	r = RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	return r;

	return amdgpu_device_indirect_rreg(adev, address, data, reg);

}



static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long flags, address, data;

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	WREG32(address, reg);

	(void)RREG32(address);

	WREG32(data, v);

	(void)RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	amdgpu_device_indirect_wreg(adev, address, data, reg, v);

}



static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags, address, data;

	u64 r;

	unsigned long address, data;

	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	/* read low 32 bit */

	WREG32(address, reg);

	(void)RREG32(address);

	r = RREG32(data);



	/* read high 32 bit*/

	WREG32(address, reg + 4);

	(void)RREG32(address);

	r |= ((u64)RREG32(data) << 32);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	return r;

	return amdgpu_device_indirect_rreg64(adev, address, data, reg);

}



static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)

{

	unsigned long flags, address, data;

	unsigned long address, data;



	address = adev->nbio.funcs->get_pcie_index_offset(adev);

	data = adev->nbio.funcs->get_pcie_data_offset(adev);



	spin_lock_irqsave(&adev->pcie_idx_lock, flags);

	/* write low 32 bit */

	WREG32(address, reg);

	(void)RREG32(address);

	WREG32(data, (u32)(v & 0xffffffffULL));

	(void)RREG32(data);



	/* write high 32 bit */

	WREG32(address, reg + 4);

	(void)RREG32(address);

	WREG32(data, (u32)(v >> 32));

	(void)RREG32(data);

	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);

	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);

}



static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

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