Commit 703d1282 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch 



This workaround for bdw and chv, is also needed for kbl A0.

References: HSD#1911519, BSID#569
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-24-git-send-email-mika.kuoppala@intel.com


(cherry picked from commit 066d4628)
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent 0e51c0bd

drivers/gpu/drm/i915/intel_lrc.c

+17 −0
Original line number Diff line number Diff line
@@ -1275,6 +1275,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, 
{

	int ret;

	struct drm_device *dev = engine->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);



	/* WaDisableCtxRestoreArbitration:skl,bxt */
@@ -1288,6 +1289,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, 
		return ret;

	index = ret;



	/* WaClearSlmSpaceAtContextSwitch:kbl */

	/* Actual scratch location is at 128 bytes offset */

	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {

		uint32_t scratch_addr

			= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;



		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));

		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |

					   PIPE_CONTROL_GLOBAL_GTT_IVB |

					   PIPE_CONTROL_CS_STALL |

					   PIPE_CONTROL_QW_WRITE));

		wa_ctx_emit(batch, index, scratch_addr);

		wa_ctx_emit(batch, index, 0);

		wa_ctx_emit(batch, index, 0);

		wa_ctx_emit(batch, index, 0);

	}

	/* Pad to end of cacheline */

	while (index % CACHELINE_DWORDS)

		wa_ctx_emit(batch, index, MI_NOOP);

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