scsi: ufs: UFS crypto API (70297a8a) · Commits · 戴 / test

drivers/scsi/ufs/Kconfig

+9 −0

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		@@ -172,3 +172,12 @@ config SCSI_UFS_EXYNOS

		Select this if you have UFS host controller on EXYNOS chipset.
		If unsure, say N.

		config SCSI_UFS_CRYPTO
		bool "UFS Crypto Engine Support"
		depends on SCSI_UFSHCD && BLK_INLINE_ENCRYPTION
		help
		Enable Crypto Engine Support in UFS.
		Enabling this makes it possible for the kernel to use the crypto
		capabilities of the UFS device (if present) to perform crypto
		operations on data being transferred to/from the device.

drivers/scsi/ufs/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -8,6 +8,7 @@ obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o
		obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o
		ufshcd-core-y += ufshcd.o ufs-sysfs.o
		ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o
		ufshcd-core-$(CONFIG_SCSI_UFS_CRYPTO) += ufshcd-crypto.o
		obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
		obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
		obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o

drivers/scsi/ufs/ufshcd-crypto.c

0 → 100644

+238 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/*
		* Copyright 2019 Google LLC
		*/

		#include "ufshcd.h"
		#include "ufshcd-crypto.h"

		/* Blk-crypto modes supported by UFS crypto */
		static const struct ufs_crypto_alg_entry {
		enum ufs_crypto_alg ufs_alg;
		enum ufs_crypto_key_size ufs_key_size;
		} ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
		[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
		.ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
		.ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
		},
		};

		static void ufshcd_program_key(struct ufs_hba *hba,
		const union ufs_crypto_cfg_entry *cfg,
		int slot)
		{
		int i;
		u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);

		ufshcd_hold(hba, false);
		/* Ensure that CFGE is cleared before programming the key */
		ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
		for (i = 0; i < 16; i++) {
		ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
		slot_offset + i * sizeof(cfg->reg_val[0]));
		}
		/* Write dword 17 */
		ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
		slot_offset + 17 * sizeof(cfg->reg_val[0]));
		/* Dword 16 must be written last */
		ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
		slot_offset + 16 * sizeof(cfg->reg_val[0]));
		ufshcd_release(hba);
		}

		static int ufshcd_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
		const struct blk_crypto_key *key,
		unsigned int slot)
		{
		struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);
		const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
		const struct ufs_crypto_alg_entry *alg =
		&ufs_crypto_algs[key->crypto_cfg.crypto_mode];
		u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
		int i;
		int cap_idx = -1;
		union ufs_crypto_cfg_entry cfg = { 0 };

		BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
		for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
		if (ccap_array[i].algorithm_id == alg->ufs_alg &&
		ccap_array[i].key_size == alg->ufs_key_size &&
		(ccap_array[i].sdus_mask & data_unit_mask)) {
		cap_idx = i;
		break;
		}
		}

		if (WARN_ON(cap_idx < 0))
		return -EOPNOTSUPP;

		cfg.data_unit_size = data_unit_mask;
		cfg.crypto_cap_idx = cap_idx;
		cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;

		if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
		/* In XTS mode, the blk_crypto_key's size is already doubled */
		memcpy(cfg.crypto_key, key->raw, key->size/2);
		memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
		key->raw + key->size/2, key->size/2);
		} else {
		memcpy(cfg.crypto_key, key->raw, key->size);
		}

		ufshcd_program_key(hba, &cfg, slot);

		memzero_explicit(&cfg, sizeof(cfg));
		return 0;
		}

		static void ufshcd_clear_keyslot(struct ufs_hba *hba, int slot)
		{
		/*
		* Clear the crypto cfg on the device. Clearing CFGE
		* might not be sufficient, so just clear the entire cfg.
		*/
		union ufs_crypto_cfg_entry cfg = { 0 };

		ufshcd_program_key(hba, &cfg, slot);
		}

		static int ufshcd_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
		const struct blk_crypto_key *key,
		unsigned int slot)
		{
		struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);

		ufshcd_clear_keyslot(hba, slot);

		return 0;
		}

		bool ufshcd_crypto_enable(struct ufs_hba *hba)
		{
		if (!(hba->caps & UFSHCD_CAP_CRYPTO))
		return false;

		/* Reset might clear all keys, so reprogram all the keys. */
		blk_ksm_reprogram_all_keys(&hba->ksm);
		return true;
		}

		static const struct blk_ksm_ll_ops ufshcd_ksm_ops = {
		.keyslot_program = ufshcd_crypto_keyslot_program,
		.keyslot_evict = ufshcd_crypto_keyslot_evict,
		};

		static enum blk_crypto_mode_num
		ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
		{
		int i;

		for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
		BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
		if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
		ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
		return i;
		}
		}
		return BLK_ENCRYPTION_MODE_INVALID;
		}

		/**
		* ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
		* fields in hba
		* @hba: Per adapter instance
		*
		* Return: 0 if crypto was initialized or is not supported, else a -errno value.
		*/
		int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
		{
		int cap_idx;
		int err = 0;
		enum blk_crypto_mode_num blk_mode_num;

		/*
		* Don't use crypto if either the hardware doesn't advertise the
		* standard crypto capability bit or if the vendor specific driver
		* hasn't advertised that crypto is supported.
		*/
		if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) \|\|
		!(hba->caps & UFSHCD_CAP_CRYPTO))
		goto out;

		hba->crypto_capabilities.reg_val =
		cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
		hba->crypto_cfg_register =
		(u32)hba->crypto_capabilities.config_array_ptr * 0x100;
		hba->crypto_cap_array =
		devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
		sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
		if (!hba->crypto_cap_array) {
		err = -ENOMEM;
		goto out;
		}

		/* The actual number of configurations supported is (CFGC+1) */
		err = blk_ksm_init(&hba->ksm,
		hba->crypto_capabilities.config_count + 1);
		if (err)
		goto out_free_caps;

		hba->ksm.ksm_ll_ops = ufshcd_ksm_ops;
		/* UFS only supports 8 bytes for any DUN */
		hba->ksm.max_dun_bytes_supported = 8;
		hba->ksm.dev = hba->dev;

		/*
		* Cache all the UFS crypto capabilities and advertise the supported
		* crypto modes and data unit sizes to the block layer.
		*/
		for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
		cap_idx++) {
		hba->crypto_cap_array[cap_idx].reg_val =
		cpu_to_le32(ufshcd_readl(hba,
		REG_UFS_CRYPTOCAP +
		cap_idx * sizeof(__le32)));
		blk_mode_num = ufshcd_find_blk_crypto_mode(
		hba->crypto_cap_array[cap_idx]);
		if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
		hba->ksm.crypto_modes_supported[blk_mode_num] \|=
		hba->crypto_cap_array[cap_idx].sdus_mask * 512;
		}

		return 0;

		out_free_caps:
		devm_kfree(hba->dev, hba->crypto_cap_array);
		out:
		/* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
		hba->caps &= ~UFSHCD_CAP_CRYPTO;
		return err;
		}

		/**
		* ufshcd_init_crypto - Initialize crypto hardware
		* @hba: Per adapter instance
		*/
		void ufshcd_init_crypto(struct ufs_hba *hba)
		{
		int slot;

		if (!(hba->caps & UFSHCD_CAP_CRYPTO))
		return;

		/* Clear all keyslots - the number of keyslots is (CFGC + 1) */
		for (slot = 0; slot < hba->crypto_capabilities.config_count + 1; slot++)
		ufshcd_clear_keyslot(hba, slot);
		}

		void ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba *hba,
		struct request_queue *q)
		{
		if (hba->caps & UFSHCD_CAP_CRYPTO)
		blk_ksm_register(&hba->ksm, q);
		}

		void ufshcd_crypto_destroy_keyslot_manager(struct ufs_hba *hba)
		{
		blk_ksm_destroy(&hba->ksm);
		}

drivers/scsi/ufs/ufshcd-crypto.h

0 → 100644

+46 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/*
		* Copyright 2019 Google LLC
		*/

		#ifndef _UFSHCD_CRYPTO_H
		#define _UFSHCD_CRYPTO_H

		#ifdef CONFIG_SCSI_UFS_CRYPTO
		#include "ufshcd.h"
		#include "ufshci.h"

		bool ufshcd_crypto_enable(struct ufs_hba *hba);

		int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba);

		void ufshcd_init_crypto(struct ufs_hba *hba);

		void ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba *hba,
		struct request_queue *q);

		void ufshcd_crypto_destroy_keyslot_manager(struct ufs_hba *hba);

		#else /* CONFIG_SCSI_UFS_CRYPTO */

		static inline bool ufshcd_crypto_enable(struct ufs_hba *hba)
		{
		return false;
		}

		static inline int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
		{
		return 0;
		}

		static inline void ufshcd_init_crypto(struct ufs_hba *hba) { }

		static inline void ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba *hba,
		struct request_queue *q) { }

		static inline void ufshcd_crypto_destroy_keyslot_manager(struct ufs_hba *hba)
		{ }

		#endif /* CONFIG_SCSI_UFS_CRYPTO */

		#endif /* _UFSHCD_CRYPTO_H */

drivers/scsi/ufs/ufshcd.h

+12 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,7 @@
		#include <linux/regulator/consumer.h>
		#include <linux/bitfield.h>
		#include <linux/devfreq.h>
		#include <linux/keyslot-manager.h>
		#include "unipro.h"

		#include <asm/irq.h>
		@@ -620,6 +621,10 @@ struct ufs_hba_variant_params {
		* @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
		* device is known or not.
		* @scsi_block_reqs_cnt: reference counting for scsi block requests
		* @crypto_capabilities: Content of crypto capabilities register (0x100)
		* @crypto_cap_array: Array of crypto capabilities
		* @crypto_cfg_register: Start of the crypto cfg array
		* @ksm: the keyslot manager tied to this hba
		*/
		struct ufs_hba {
		void __iomem *mmio_base;
		@@ -742,6 +747,13 @@ struct ufs_hba {
		bool wb_buf_flush_enabled;
		bool wb_enabled;
		struct delayed_work rpm_dev_flush_recheck_work;

		#ifdef CONFIG_SCSI_UFS_CRYPTO
		union ufs_crypto_capabilities crypto_capabilities;
		union ufs_crypto_cap_entry *crypto_cap_array;
		u32 crypto_cfg_register;
		struct blk_keyslot_manager ksm;
		#endif
		};

		/* Returns true if clocks can be gated. Otherwise false */

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