Commit 7026a5fd authored by Alexander Usyskin's avatar Alexander Usyskin Committed by Greg Kroah-Hartman
Browse files

mei: define dma ring buffer sizes for PCH12 HW and newer



Define dma ring buffer sizes for PCH12 (CLN HW and newer)

Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c2bd9fc1
Loading
Loading
Loading
Loading
+13 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@
#include <linux/kthread.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>

#include "mei_dev.h"
#include "hbm.h"
@@ -1389,6 +1390,11 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
	.fw_status.status[4] = PCI_CFG_HFS_5,   \
	.fw_status.status[5] = PCI_CFG_HFS_6

#define MEI_CFG_DMA_128 \
	.dma_size[DMA_DSCR_HOST] = SZ_128K, \
	.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
	.dma_size[DMA_DSCR_CTRL] = PAGE_SIZE

/* ICH Legacy devices */
static const struct mei_cfg mei_me_ich_cfg = {
	MEI_CFG_ICH_HFS,
@@ -1421,6 +1427,12 @@ static const struct mei_cfg mei_me_pch8_sps_cfg = {
	MEI_CFG_FW_SPS,
};

/* Cannon Lake and newer devices */
static const struct mei_cfg mei_me_pch12_cfg = {
	MEI_CFG_PCH8_HFS,
	MEI_CFG_DMA_128,
};

/*
 * mei_cfg_list - A list of platform platform specific configurations.
 * Note: has to be synchronized with  enum mei_cfg_idx.
@@ -1433,6 +1445,7 @@ static const struct mei_cfg *const mei_cfg_list[] = {
	[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
	[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
	[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
	[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
};

const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
+4 −0
Original line number Diff line number Diff line
@@ -31,10 +31,12 @@
 *
 * @fw_status: FW status
 * @quirk_probe: device exclusion quirk
 * @dma_size: device DMA buffers size
 */
struct mei_cfg {
	const struct mei_fw_status fw_status;
	bool (*quirk_probe)(struct pci_dev *pdev);
	size_t dma_size[DMA_DSCR_NUM];
};


@@ -80,6 +82,7 @@ struct mei_me_hw {
 * @MEI_ME_PCH8_SPS_CFG:   Platform Controller Hub Gen8 and newer
 *                         servers platforms with quirk for
 *                         SPS firmware exclusion.
 * @MEI_ME_PCH12_CFG:      Platform Controller Hub Gen12 and newer
 * @MEI_ME_NUM_CFG:        Upper Sentinel.
 */
enum mei_cfg_idx {
@@ -90,6 +93,7 @@ enum mei_cfg_idx {
	MEI_ME_PCH_CPT_PBG_CFG,
	MEI_ME_PCH8_CFG,
	MEI_ME_PCH8_SPS_CFG,
	MEI_ME_PCH12_CFG,
	MEI_ME_NUM_CFG,
};