Commit 7025fdbe authored by Florian Fainelli's avatar Florian Fainelli Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events 



The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:

- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)

Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sean V Kelley <seanvk.dev@oregontracks.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 93fe8f1e

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json

0 → 100644
+179 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1D_CACHE_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD",

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN",

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_SHARED",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NORMAL",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_PERIPH",

    },

    {

        "ArchStdEvent": "MEM_ACCESS_RD",

    },

    {

        "ArchStdEvent": "MEM_ACCESS_WR",

    },

    {

        "ArchStdEvent": "UNALIGNED_LD_SPEC",

    },

    {

        "ArchStdEvent": "UNALIGNED_ST_SPEC",

    },

    {

        "ArchStdEvent": "UNALIGNED_LDST_SPEC",

    },

    {

        "ArchStdEvent": "LDREX_SPEC",

    },

    {

        "ArchStdEvent": "STREX_PASS_SPEC",

    },

    {

        "ArchStdEvent": "STREX_FAIL_SPEC",

    },

    {

        "ArchStdEvent": "LD_SPEC",

    },

    {

        "ArchStdEvent": "ST_SPEC",

    },

    {

        "ArchStdEvent": "LDST_SPEC",

    },

    {

        "ArchStdEvent": "DP_SPEC",

    },

    {

        "ArchStdEvent": "ASE_SPEC",

    },

    {

        "ArchStdEvent": "VFP_SPEC",

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC",

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC",

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC",

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC",

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC",

    },

    {

        "ArchStdEvent": "ISB_SPEC",

    },

    {

        "ArchStdEvent": "DSB_SPEC",

    },

    {

        "ArchStdEvent": "DMB_SPEC",

    },

    {

        "ArchStdEvent": "EXC_UNDEF",

    },

    {

        "ArchStdEvent": "EXC_SVC",

    },

    {

        "ArchStdEvent": "EXC_PABORT",

    },

    {

        "ArchStdEvent": "EXC_DABORT",

    },

    {

        "ArchStdEvent": "EXC_IRQ",

    },

    {

        "ArchStdEvent": "EXC_FIQ",

    },

    {

        "ArchStdEvent": "EXC_SMC",

    },

    {

        "ArchStdEvent": "EXC_HVC",

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER",

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ",

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ",

    },

    {

        "ArchStdEvent": "RC_LD_SPEC",

    },

    {

        "ArchStdEvent": "RC_ST_SPEC",

    },

]

tools/perf/pmu-events/arch/arm64/mapfile.csv

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#Family-model,Version,Filename,EventType

0x00000000410fd030,v1,arm/cortex-a53,core

0x00000000420f1000,v1,arm/cortex-a53,core

0x00000000410fd070,v1,arm/cortex-a57-a72,core

0x00000000410fd080,v1,arm/cortex-a57-a72,core

0x00000000420f5160,v1,cavium/thunderx2,core

0x00000000430f0af0,v1,cavium/thunderx2,core

0x00000000480fd010,v1,hisilicon/hip08,core

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