MIPS: Get rid of hard-coded values for Malta PIIX4 fixups (70002f76) · Commits · 戴 / test

arch/mips/include/asm/mips-boards/piix4.h

+23 −0

Original line number	Diff line number	Diff line
		/*
		* Carsten Langgaard, carstenl@mips.com
		* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
		* Copyright (C) 2013 Imagination Technologies Ltd.
		*
		* This program is free software; you can distribute it and/or modify it
		* under the terms of the GNU General Public License (Version 2) as
		@@ -20,6 +21,28 @@
		#ifndef __ASM_MIPS_BOARDS_PIIX4_H
		#define __ASM_MIPS_BOARDS_PIIX4_H

		/* PIRQX Route Control */
		#define PIIX4_FUNC0_PIRQRC 0x60
		#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
		#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
		#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
		/* Top Of Memory */
		#define PIIX4_FUNC0_TOM 0x69
		#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
		/* Deterministic Latency Control */
		#define PIIX4_FUNC0_DLC 0x82
		#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
		#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
		#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)

		/* IDE Timing */
		#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
		#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
		#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
		#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
		#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
		#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)

		/************************************************************************
		* IO register offsets
		************************************************************************/

arch/mips/pci/fixup-malta.c

+23 −13

Original line number	Diff line number	Diff line
		#include <linux/init.h>
		#include <linux/pci.h>
		#include <asm/mips-boards/piix4.h>

		/* PCI interrupt pins */
		#define PCIA 1
		@@ -53,7 +54,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
		static void malta_piix_func0_fixup(struct pci_dev *pdev)
		{
		unsigned char reg_val;
		static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */
		/* PIIX PIRQC[A:D] irq mappings */
		static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
		0, 0, 0, 3,
		4, 5, 6, 7,
		0, 9, 10, 11,
		@@ -63,11 +65,12 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)

		/* Interrogate PIIX4 to get PCI IRQ mapping */
		for (i = 0; i <= 3; i++) {
		pci_read_config_byte(pdev, 0x60+i, &reg_val);
		if (reg_val & 0x80)
		pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
		if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
		pci_irq[PCIA+i] = 0; /* Disabled */
		else
		pci_irq[PCIA+i] = piixirqmap[reg_val & 15];
		pci_irq[PCIA+i] = piixirqmap[reg_val &
		PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
		}

		/* Done by YAMON 2.00 onwards */
		@@ -76,8 +79,9 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
		* Set top of main memory accessible by ISA or DMA
		* devices to 16 Mb.
		*/
		pci_read_config_byte(pdev, 0x69, &reg_val);
		pci_write_config_byte(pdev, 0x69, reg_val \| 0xf0);
		pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
		pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val \|
		PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
		}
		}

		@@ -93,10 +97,14 @@ static void malta_piix_func1_fixup(struct pci_dev *pdev)
		/*
		* IDE Decode enable.
		*/
		pci_read_config_byte(pdev, 0x41, &reg_val);
		pci_write_config_byte(pdev, 0x41, reg_val\|0x80);
		pci_read_config_byte(pdev, 0x43, &reg_val);
		pci_write_config_byte(pdev, 0x43, reg_val\|0x80);
		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
		&reg_val);
		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
		reg_val\|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
		&reg_val);
		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
		reg_val\|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
		}
		}

		@@ -108,10 +116,12 @@ static void quirk_dlcsetup(struct pci_dev *dev)
		{
		u8 odlc, ndlc;

		(void) pci_read_config_byte(dev, 0x82, &odlc);
		(void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
		/* Enable passive releases and delayed transaction */
		ndlc = odlc \| 7;
		(void) pci_write_config_byte(dev, 0x82, ndlc);
		ndlc = odlc \| PIIX4_FUNC0_DLC_USBPR_EN \|
		PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN \|
		PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
		(void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
		}

		DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,

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