drm/amd/display: fix surface update sequence (6fd3583b) · Commits · 戴 / test

An earlier change added update of interdependent dlg/ttu params for pipes not being updated in the current call. The code fails to check if the other pipes are actually active yet causing an assert. This change adds a check for surface presence on the pipes before updating the interdepenednt params. Signed-off-by:

Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:

Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -2357,7 +2357,8 @@ static void dcn10_apply_ctx_for_surface(
		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

		/* Skip inactive pipes and ones already updated */
		if (!pipe_ctx->stream \|\| pipe_ctx->stream == stream)
		if (!pipe_ctx->stream \|\| pipe_ctx->stream == stream
		\|\| !pipe_ctx->plane_state)
		continue;

		pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
		@@ -2371,7 +2372,8 @@ static void dcn10_apply_ctx_for_surface(
		for (i = 0; i < dc->res_pool->pipe_count; i++) {
		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

		if (!pipe_ctx->stream \|\| pipe_ctx->stream == stream)
		if (!pipe_ctx->stream \|\| pipe_ctx->stream == stream
		\|\| !pipe_ctx->plane_state)
		continue;

		dcn10_pipe_control_lock(dc, pipe_ctx, false);

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