usb: dwc2: Fix kernel doc's warnings. (6fb914d7) · Commits · 戴 / test

drivers/usb/dwc2/core.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -419,6 +419,8 @@ static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
		/**
		* dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
		* filter is enabled.
		*
		* @hsotg: Programming view of DWC_otg controller
		*/
		static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
		{
		@@ -564,6 +566,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
		* If a force is done, it requires a IDDIG debounce filter delay if
		* the filter is configured and enabled. We poll the current mode of
		* the controller to account for this delay.
		*
		* @hsotg: Programming view of DWC_otg controller
		* @host: Host mode flag
		*/
		void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
		{
		@@ -610,6 +615,8 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
		* or not because the value of the connector ID status is affected by
		* the force mode. We only need to call this once during probe if
		* dr_mode == OTG.
		*
		* @hsotg: Programming view of DWC_otg controller
		*/
		static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
		{

drivers/usb/dwc2/core.h

+137 −33

Original line number	Diff line number	Diff line
		@@ -164,12 +164,11 @@ struct dwc2_hsotg_req;
		* and has yet to be completed (maybe due to data move, or simply
		* awaiting an ack from the core all the data has been completed).
		* @debugfs: File entry for debugfs file for this endpoint.
		* @lock: State lock to protect contents of endpoint.
		* @dir_in: Set to true if this endpoint is of the IN direction, which
		* means that it is sending data to the Host.
		* @index: The index for the endpoint registers.
		* @mc: Multi Count - number of transactions per microframe
		* @interval - Interval for periodic endpoints, in frames or microframes.
		* @interval: Interval for periodic endpoints, in frames or microframes.
		* @name: The name array passed to the USB core.
		* @halted: Set if the endpoint has been halted.
		* @periodic: Set if this is a periodic ep, such as Interrupt
		@@ -182,6 +181,7 @@ struct dwc2_hsotg_req;
		* @compl_desc: index of next descriptor to be completed by xFerComplete
		* @total_data: The total number of data bytes done.
		* @fifo_size: The size of the FIFO (for periodic IN endpoints)
		* @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
		* @fifo_load: The amount of data loaded into the FIFO (periodic IN)
		* @last_load: The offset of data for the last start of request.
		* @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
		@@ -380,9 +380,12 @@ enum dwc2_ep0_state {
		* is FS.
		* 0 - No (default)
		* 1 - Yes
		* @ipg_isoc_en Indicates the IPG supports is enabled or disabled.
		* @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
		* 0 - Disable (default)
		* 1 - Enable
		* @acg_enable: For enabling Active Clock Gating in the controller
		* 0 - No
		* 1 - Yes
		* @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
		* 0 - No (default)
		* 1 - Yes
		@@ -552,7 +555,7 @@ struct dwc2_core_params {
		*
		* The values that are not in dwc2_core_params are documented below.
		*
		* @op_mode Mode of Operation
		* @op_mode: Mode of Operation
		* 0 - HNP- and SRP-Capable OTG (Host & Device)
		* 1 - SRP-Capable OTG (Host & Device)
		* 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
		@@ -560,49 +563,102 @@ struct dwc2_core_params {
		* 4 - Non-OTG Device
		* 5 - SRP-Capable Host
		* 6 - Non-OTG Host
		* @arch Architecture
		* @arch: Architecture
		* 0 - Slave only
		* 1 - External DMA
		* 2 - Internal DMA
		* @ipg_isoc_en This feature indicates that the controller supports
		* @ipg_isoc_en: This feature indicates that the controller supports
		* the worst-case scenario of Rx followed by Rx
		* Interpacket Gap (IPG) (32 bitTimes) as per the utmi
		* specification for any token following ISOC OUT token.
		* 0 - Don't support
		* 1 - Support
		* @power_optimized Are power optimizations enabled?
		* @num_dev_ep Number of device endpoints available
		* @num_dev_in_eps Number of device IN endpoints available
		* @num_dev_perio_in_ep Number of device periodic IN endpoints
		* @power_optimized: Are power optimizations enabled?
		* @num_dev_ep: Number of device endpoints available
		* @num_dev_in_eps: Number of device IN endpoints available
		* @num_dev_perio_in_ep: Number of device periodic IN endpoints
		* available
		* @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
		* @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
		* Depth
		* 0 to 30
		* @host_perio_tx_q_depth
		* @host_perio_tx_q_depth:
		* Host Mode Periodic Request Queue Depth
		* 2, 4 or 8
		* @nperio_tx_q_depth
		* @nperio_tx_q_depth:
		* Non-Periodic Request Queue Depth
		* 2, 4 or 8
		* @hs_phy_type High-speed PHY interface type
		* @hs_phy_type: High-speed PHY interface type
		* 0 - High-speed interface not supported
		* 1 - UTMI+
		* 2 - ULPI
		* 3 - UTMI+ and ULPI
		* @fs_phy_type Full-speed PHY interface type
		* @fs_phy_type: Full-speed PHY interface type
		* 0 - Full speed interface not supported
		* 1 - Dedicated full speed interface
		* 2 - FS pins shared with UTMI+ pins
		* 3 - FS pins shared with ULPI pins
		* @total_fifo_size: Total internal RAM for FIFOs (bytes)
		* @hibernation Is hibernation enabled?
		* @utmi_phy_data_width UTMI+ PHY data width
		* @hibernation: Is hibernation enabled?
		* @utmi_phy_data_width: UTMI+ PHY data width
		* 0 - 8 bits
		* 1 - 16 bits
		* 2 - 8 or 16 bits
		* @snpsid: Value from SNPSID register
		* @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
		* @g_tx_fifo_size[] Power-on values of TxFIFO sizes
		* @g_tx_fifo_size: Power-on values of TxFIFO sizes
		* @dma_desc_enable: When DMA mode is enabled, specifies whether to use
		* address DMA mode or descriptor DMA mode for accessing
		* the data FIFOs. The driver will automatically detect the
		* value for this if none is specified.
		* 0 - Address DMA
		* 1 - Descriptor DMA (default, if available)
		* @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
		* 1 - Allow dynamic FIFO sizing (default, if available)
		* @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
		* are enabled for non-periodic IN endpoints in device
		* mode.
		* @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
		* in host mode when dynamic FIFO sizing is enabled
		* 16 to 32768
		* Actual maximum value is autodetected and also
		* the default.
		* @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
		* host mode when dynamic FIFO sizing is enabled
		* 16 to 32768
		* Actual maximum value is autodetected and also
		* the default.
		* @max_transfer_size: The maximum transfer size supported, in bytes
		* 2047 to 65,535
		* Actual maximum value is autodetected and also
		* the default.
		* @max_packet_count: The maximum number of packets in a transfer
		* 15 to 511
		* Actual maximum value is autodetected and also
		* the default.
		* @host_channels: The number of host channel registers to use
		* 1 to 16
		* Actual maximum value is autodetected and also
		* the default.
		* @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
		* in device mode when dynamic FIFO sizing is enabled
		* 16 to 32768
		* Actual maximum value is autodetected and also
		* the default.
		* @i2c_enable: Specifies whether to use the I2Cinterface for a full
		* speed PHY. This parameter is only applicable if phy_type
		* is FS.
		* 0 - No (default)
		* 1 - Yes
		* @acg_enable: For enabling Active Clock Gating in the controller
		* 0 - Disable
		* 1 - Enable
		* @lpm_mode: For enabling Link Power Management in the controller
		* 0 - Disable
		* 1 - Enable
		* @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
		* FIFO sizing is enabled 16 to 32768
		* Actual maximum value is autodetected and also
		* the default.
		*/
		struct dwc2_hw_params {
		unsigned op_mode:3;
		@@ -653,7 +709,11 @@ struct dwc2_hw_params {
		* @gi2cctl: Backup of GI2CCTL register
		* @glpmcfg: Backup of GLPMCFG register
		* @gdfifocfg: Backup of GDFIFOCFG register
		* @pcgcctl: Backup of PCGCCTL register
		* @pcgcctl1: Backup of PCGCCTL1 register
		* @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
		* @gpwrdn: Backup of GPWRDN register
		* @valid: True if registers values backuped.
		*/
		struct dwc2_gregs_backup {
		u32 gotgctl;
		@@ -686,6 +746,7 @@ struct dwc2_gregs_backup {
		* @doeptsiz: Backup of DOEPTSIZ register
		* @doepdma: Backup of DOEPDMA register
		* @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
		* @valid: True if registers values backuped.
		*/
		struct dwc2_dregs_backup {
		u32 dcfg;
		@@ -709,9 +770,10 @@ struct dwc2_dregs_backup {
		* @hcfg: Backup of HCFG register
		* @haintmsk: Backup of HAINTMSK register
		* @hcintmsk: Backup of HCINTMSK register
		* @hptr0: Backup of HPTR0 register
		* @hprt0: Backup of HPTR0 register
		* @hfir: Backup of HFIR register
		* @hptxfsiz: Backup of HPTXFSIZ register
		* @valid: True if registers values backuped.
		*/
		struct dwc2_hregs_backup {
		u32 hcfg;
		@@ -811,7 +873,7 @@ struct dwc2_hregs_backup {
		* @regs: Pointer to controller regs
		* @hw_params: Parameters that were autodetected from the
		* hardware registers
		* @core_params: Parameters that define how the core should be configured
		* @params: Parameters that define how the core should be configured
		* @op_state: The operational State, during transitions (a_host=>
		* a_peripheral and b_device=>b_host) this may not match
		* the core, but allows the software to determine
		@@ -820,9 +882,9 @@ struct dwc2_hregs_backup {
		* - USB_DR_MODE_PERIPHERAL
		* - USB_DR_MODE_HOST
		* - USB_DR_MODE_OTG
		* @hcd_enabled Host mode sub-driver initialization indicator.
		* @gadget_enabled Peripheral mode sub-driver initialization indicator.
		* @ll_hw_enabled Status of low-level hardware resources.
		* @hcd_enabled: Host mode sub-driver initialization indicator.
		* @gadget_enabled: Peripheral mode sub-driver initialization indicator.
		* @ll_hw_enabled: Status of low-level hardware resources.
		* @hibernated: True if core is hibernated
		* @frame_number: Frame number read from the core. For both device
		* and host modes. The value ranges are from 0
		@@ -846,13 +908,25 @@ struct dwc2_hregs_backup {
		* interrupt
		* @wkp_timer: Timer object for handling Wakeup Detected interrupt
		* @lx_state: Lx state of connected device
		* @gregs_backup: Backup of global registers during suspend
		* @dregs_backup: Backup of device registers during suspend
		* @hregs_backup: Backup of host registers during suspend
		* @gr_backup: Backup of global registers during suspend
		* @dr_backup: Backup of device registers during suspend
		* @hr_backup: Backup of host registers during suspend
		*
		* These are for host mode:
		*
		* @flags: Flags for handling root port state changes
		* @flags.d32: Contain all root port flags
		* @flags.b: Separate root port flags from each other
		* @flags.b.port_connect_status_change: True if root port connect status
		* changed
		* @flags.b.port_connect_status: True if device connected to root port
		* @flags.b.port_reset_change: True if root port reset status changed
		* @flags.b.port_enable_change: True if root port enable status changed
		* @flags.b.port_suspend_change: True if root port suspend status changed
		* @flags.b.port_over_current_change: True if root port over current state
		* changed.
		* @flags.b.port_l1_change: True if root port l1 status changed
		* @flags.b.reserved: Reserved bits of root port register
		* @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
		* Transfers associated with these QHs are not currently
		* assigned to a host channel.
		@@ -861,6 +935,9 @@ struct dwc2_hregs_backup {
		* assigned to a host channel.
		* @non_periodic_qh_ptr: Pointer to next QH to process in the active
		* non-periodic schedule
		* @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
		* Transfers associated with these QHs are not currently
		* assigned to a host channel.
		* @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
		* list of QHs for periodic transfers that are _not_
		* scheduled for the next frame. Each QH in the list has an
		@@ -910,8 +987,8 @@ struct dwc2_hregs_backup {
		* host channel is available for non-periodic transactions.
		* @non_periodic_channels: Number of host channels assigned to non-periodic
		* transfers
		* @available_host_channels Number of host channels available for the microframe
		* scheduler to use
		* @available_host_channels: Number of host channels available for the
		* microframe scheduler to use
		* @hc_ptr_array: Array of pointers to the host channel descriptors.
		* Allows accessing a host channel descriptor given the
		* host channel number. This is useful in interrupt
		@@ -934,9 +1011,6 @@ struct dwc2_hregs_backup {
		* @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
		* @num_of_eps: Number of available EPs (excluding EP0)
		* @debug_root: Root directrory for debugfs.
		* @debug_file: Main status file for debugfs.
		* @debug_testmode: Testmode status file for debugfs.
		* @debug_fifo: FIFO status file for debugfs.
		* @ep0_reply: Request used for ep0 reply.
		* @ep0_buff: Buffer for EP0 reply data, if needed.
		* @ctrl_buff: Buffer for EP0 control requests.
		@@ -951,7 +1025,37 @@ struct dwc2_hregs_backup {
		* @ctrl_in_desc: EP0 IN data phase desc chain pointer
		* @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
		* @ctrl_out_desc: EP0 OUT data phase desc chain pointer
		* @eps: The endpoints being supplied to the gadget framework
		* @irq: Interrupt request line number
		* @clk: Pointer to otg clock
		* @reset: Pointer to dwc2 reset controller
		* @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
		* @regset: A pointer to a struct debugfs_regset32, which contains
		* a pointer to an array of register definitions, the
		* array size and the base address where the register bank
		* is to be found.
		* @bus_suspended: True if bus is suspended
		* @last_frame_num: Number of last frame. Range from 0 to 32768
		* @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
		* defined, for missed SOFs tracking. Array holds that
		* frame numbers, which not equal to last_frame_num +1
		* @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
		* defined, for missed SOFs tracking.
		* If current_frame_number != last_frame_num+1
		* then last_frame_num added to this array
		* @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
		* @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
		* 0 - if missed SOFs frame numbers not dumbed
		* @fifo_mem: Total internal RAM for FIFOs (bytes)
		* @fifo_map: Each bit intend for concrete fifo. If that bit is set,
		* then that fifo is used
		* @gadget: Represents a usb slave device
		* @connected: Used in slave mode. True if device connected with host
		* @eps_in: The IN endpoints being supplied to the gadget framework
		* @eps_out: The OUT endpoints being supplied to the gadget framework
		* @new_connection: Used in host mode. True if there are new connected
		* device
		* @enabled: Indicates the enabling state of controller
		*
		*/
		struct dwc2_hsotg {
		struct device *dev;

drivers/usb/dwc2/debug.h

+1 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/**
		/*
		* debug.h - Designware USB2 DRD controller debug header
		*
		* Copyright (C) 2015 Intel Corporation

drivers/usb/dwc2/debugfs.c

+10 −9

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/**
		/*
		* debugfs.c - Designware USB2 DRD controller debugfs
		*
		* Copyright (C) 2015 Intel Corporation
		@@ -16,12 +16,13 @@

		#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) \|\| \
		IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)

		/**
		* testmode_write - debugfs: change usb test mode
		* @seq: The seq file to write to.
		* @v: Unused parameter.
		*
		* This debugfs entry modify the current usb test mode.
		* testmode_write() - change usb test mode state.
		* @file: The file to write to.
		* @ubuf: The buffer where user wrote.
		* @count: The ubuf size.
		* @ppos: Unused parameter.
		*/
		static ssize_t testmode_write(struct file file, const char __user ubuf, size_t
		count, loff_t *ppos)
		@@ -55,9 +56,9 @@ static ssize_t testmode_write(struct file file, const char __user ubuf, size_t
		}

		/**
		* testmode_show - debugfs: show usb test mode state
		* @seq: The seq file to write to.
		* @v: Unused parameter.
		* testmode_show() - debugfs: show usb test mode state
		* @s: The seq file to write to.
		* @unused: Unused parameter.
		*
		* This debugfs entry shows which usb test mode is currently enabled.
		*/

drivers/usb/dwc2/gadget.c

+20 −9

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/**
		/*
		* Copyright (c) 2011 Samsung Electronics Co., Ltd.
		* http://www.samsung.com
		*
		@@ -107,7 +107,6 @@ static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
		/**
		* dwc2_gadget_incr_frame_num - Increments the targeted frame number.
		* @hs_ep: The endpoint
		* @increment: The value to increment by
		*
		* This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
		* If an overrun occurs it will wrap the value and set the frame_overrun flag.
		@@ -190,6 +189,8 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,

		/**
		* dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
		*
		* @hsotg: Programming view of the DWC_otg controller
		*/
		int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
		{
		@@ -204,6 +205,8 @@ int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
		/**
		* dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
		* device mode TX FIFOs
		*
		* @hsotg: Programming view of the DWC_otg controller
		*/
		int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
		{
		@@ -227,6 +230,8 @@ int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
		/**
		* dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
		* TX FIFOs
		*
		* @hsotg: Programming view of the DWC_otg controller
		*/
		int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
		{
		@@ -327,6 +332,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
		}

		/**
		* dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
		* @ep: USB endpoint to allocate request for.
		* @flags: Allocation flags
		*
		@@ -2424,6 +2430,7 @@ static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
		* @ep: The index number of the endpoint
		* @mps: The maximum packet size in bytes
		* @mc: The multicount value
		* @dir_in: True if direction is in.
		*
		* Configure the maximum packet size for the given endpoint, updating
		* the hardware control registers to reflect this.
		@@ -2723,7 +2730,7 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)

		/**
		* dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
		* @hs_ep: The endpoint on which interrupt is asserted.
		* @ep: The endpoint on which interrupt is asserted.
		*
		* This is starting point for ISOC-OUT transfer, synchronization done with
		* first out token received from host while corresponding EP is disabled.
		@@ -3183,6 +3190,7 @@ static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
		/**
		* dwc2_hsotg_core_init - issue softreset to the core
		* @hsotg: The device state
		* @is_usb_reset: Usb resetting flag
		*
		* Issue a soft reset to the core, and await the core finishing it.
		*/
		@@ -4289,7 +4297,6 @@ err:
		/**
		* dwc2_hsotg_udc_stop - stop the udc
		* @gadget: The usb gadget state
		* @driver: The usb gadget driver
		*
		* Stop udc hw block and stay tunned for future transmissions
		*/
		@@ -4441,6 +4448,7 @@ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
		* @hsotg: The device state.
		* @hs_ep: The endpoint to be initialised.
		* @epnum: The endpoint number
		* @dir_in: True if direction is in.
		*
		* Initialise the given endpoint (as part of the probe and device state
		* creation) to give to the gadget driver. Setup the endpoint name, any
		@@ -4514,7 +4522,7 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,

		/**
		* dwc2_hsotg_hw_cfg - read HW configuration registers
		* @param: The device state
		* @hsotg: Programming view of the DWC_otg controller
		*
		* Read the USB core HW configuration registers
		*/
		@@ -4570,7 +4578,8 @@ static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)

		/**
		* dwc2_hsotg_dump - dump state of the udc
		* @param: The device state
		* @hsotg: Programming view of the DWC_otg controller
		*
		*/
		static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
		{
		@@ -4621,7 +4630,8 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)

		/**
		* dwc2_gadget_init - init function for gadget
		* @dwc2: The data structure for the DWC2 driver.
		* @hsotg: Programming view of the DWC_otg controller
		*
		*/
		int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
		{
		@@ -4718,7 +4728,8 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg)

		/**
		* dwc2_hsotg_remove - remove function for hsotg driver
		* @pdev: The platform information for the driver
		* @hsotg: Programming view of the DWC_otg controller
		*
		*/
		int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
		{
		@@ -4999,7 +5010,7 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
		*
		* @hsotg: Programming view of the DWC_otg controller
		* @rem_wakeup: indicates whether resume is initiated by Device or Host.
		* @param reset: indicates whether resume is initiated by Reset.
		* @reset: indicates whether resume is initiated by Reset.
		*
		* Return non-zero if failed to exit from hibernation.
		*/

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