Commit 6f7343d4 authored by andrea merello's avatar andrea merello Committed by John W. Linville
Browse files

rtl818x: change misleading names for few register bit definitions 



In rtl8180/rtl8187 drivers, few register bit definitions have
names of form FOOBAR_SHIFT, suggesting they should be used as
shift offset, for example
reg |= (1 << ENABLE_FOO_SHIFT).

However they are actually defined as (1 << x) and thus they are
used (correctly) like
reg |= ENABLE_FOO_SHIFT;

This patch kills the misleading _SHIFT suffix.

Signed-off-by: default avatarandrea merello <andrea.merello@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent bafc20a6

drivers/net/wireless/rtl818x/rtl8180/dev.c

+4 −4
Original line number Diff line number Diff line
@@ -602,13 +602,13 @@ static int rtl8180_start(struct ieee80211_hw *dev) 


	if (priv->r8185) {

		reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);

		reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;

		reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;

		reg &= ~RTL818X_CW_CONF_PERPACKET_CW;

		reg |= RTL818X_CW_CONF_PERPACKET_RETRY;

		rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);



		reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;

		reg |=  RTL818X_TX_AGC_CTL_FEEDBACK_ANT;

		rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);

drivers/net/wireless/rtl818x/rtl8187/dev.c

+7 −7
Original line number Diff line number Diff line
@@ -785,7 +785,7 @@ static int rtl8187b_init_hw(struct ieee80211_hw *dev) 
	rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);



	reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);

	reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;

	reg |= RTL818X_CW_CONF_PERPACKET_RETRY;

	rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);



	/* Auto Rate Fallback Register (ARFR): 1M-54M setting */
@@ -943,8 +943,8 @@ static int rtl8187_start(struct ieee80211_hw *dev) 
		rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);



		reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;

		reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;

		reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;

		rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
@@ -986,13 +986,13 @@ static int rtl8187_start(struct ieee80211_hw *dev) 
	rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);



	reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);

	reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;

	reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;

	reg &= ~RTL818X_CW_CONF_PERPACKET_CW;

	reg |= RTL818X_CW_CONF_PERPACKET_RETRY;

	rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);



	reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);

	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;

	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;

	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;

	reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;

	reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;

	rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);

drivers/net/wireless/rtl818x/rtl818x.h

+5 −5
Original line number Diff line number Diff line
@@ -144,8 +144,8 @@ struct rtl818x_csr { 
	__le32	HSSI_PARA;

	u8	reserved_13[4];

	u8	TX_AGC_CTL;

#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT		(1 << 0)

#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT	(1 << 1)

#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN	(1 << 0)

#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL	(1 << 1)

#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT		(1 << 2)

	u8	TX_GAIN_CCK;

	u8	TX_GAIN_OFDM;
@@ -158,8 +158,8 @@ struct rtl818x_csr { 
	u8	SLOT;

	u8	reserved_16[5];

	u8	CW_CONF;

#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT	(1 << 0)

#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT	(1 << 1)

#define RTL818X_CW_CONF_PERPACKET_CW	(1 << 0)

#define RTL818X_CW_CONF_PERPACKET_RETRY	(1 << 1)

	u8	CW_VAL;

	u8	RATE_FALLBACK;

#define RTL818X_RATE_FALLBACK_ENABLE	(1 << 7)

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