Commit 6f68fbaa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx 

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
  DMAENGINE: extend the control command to include an arg
  async_tx: trim dma_async_tx_descriptor in 'no channel switch' case
  DMAENGINE: DMA40 fix for allocation of logical channel 0
  DMAENGINE: DMA40 support paused channel status
  dmaengine: mpc512x: Use resource_size
  DMA ENGINE: Do not reset 'private' of channel
  ioat: Remove duplicated devm_kzalloc() calls for ioatdma_device
  ioat3: disable cacheline-unaligned transfers for raid operations
  ioat2,3: convert to producer/consumer locking
  ioat: convert to circ_buf
  DMAENGINE: Support for ST-Ericssons DMA40 block v3
  async_tx: use of kzalloc/kfree requires the include of slab.h
  dmaengine: provide helper for setting txstate
  DMAENGINE: generic channel status v2
  DMAENGINE: generic slave control v2
  dma: timb-dma: Update comment and fix compiler warning
  dma: Add timb-dma
  DMAENGINE: COH 901 318 fix bytesleft
  DMAENGINE: COH 901 318 rename confusing vars
parents 6e451397 0b28330e

arch/arm/mach-u300/include/mach/coh901318.h

+0 −21
Original line number Diff line number Diff line
@@ -102,27 +102,6 @@ struct coh901318_platform { 
	const int max_channels;

};



/**

 * coh901318_get_bytes_left() - Get number of bytes left on a current transfer

 * @chan: dma channel handle

 * return number of bytes left, or negative on error

 */

u32 coh901318_get_bytes_left(struct dma_chan *chan);



/**

 * coh901318_stop() - Stops dma transfer

 * @chan: dma channel handle

 * return 0 on success otherwise negative value

 */

void coh901318_stop(struct dma_chan *chan);



/**

 * coh901318_continue() - Resumes a stopped dma transfer

 * @chan: dma channel handle

 * return 0 on success otherwise negative value

 */

void coh901318_continue(struct dma_chan *chan);



/**

 * coh901318_filter_id() - DMA channel filter function

 * @chan: dma channel handle

arch/arm/plat-nomadik/include/plat/ste_dma40.h

0 → 100644
+239 −0
Original line number Diff line number Diff line 
/*

 * arch/arm/plat-nomadik/include/plat/ste_dma40.h

 *

 * Copyright (C) ST-Ericsson 2007-2010

 * License terms: GNU General Public License (GPL) version 2

 * Author: Per Friden <per.friden@stericsson.com>

 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>

 */





#ifndef STE_DMA40_H

#define STE_DMA40_H



#include <linux/dmaengine.h>

#include <linux/workqueue.h>

#include <linux/interrupt.h>

#include <linux/dmaengine.h>



/* dev types for memcpy */

#define STEDMA40_DEV_DST_MEMORY (-1)

#define	STEDMA40_DEV_SRC_MEMORY (-1)



/*

 * Description of bitfields of channel_type variable is available in

 * the info structure.

 */



/* Priority */

#define STEDMA40_INFO_PRIO_TYPE_POS 2

#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)

#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)



/* Mode  */

#define STEDMA40_INFO_CH_MODE_TYPE_POS 6

#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)

#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)

#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)



/* Mode options */

#define STEDMA40_INFO_CH_MODE_OPT_POS 8

#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)



/* Interrupt */

#define STEDMA40_INFO_TIM_POS 10

#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)

#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)



/* End of channel_type configuration */



#define STEDMA40_ESIZE_8_BIT  0x0

#define STEDMA40_ESIZE_16_BIT 0x1

#define STEDMA40_ESIZE_32_BIT 0x2

#define STEDMA40_ESIZE_64_BIT 0x3



/* The value 4 indicates that PEN-reg shall be set to 0 */

#define STEDMA40_PSIZE_PHY_1  0x4

#define STEDMA40_PSIZE_PHY_2  0x0

#define STEDMA40_PSIZE_PHY_4  0x1

#define STEDMA40_PSIZE_PHY_8  0x2

#define STEDMA40_PSIZE_PHY_16 0x3



/*

 * The number of elements differ in logical and

 * physical mode

 */

#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2

#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4

#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8

#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16



enum stedma40_flow_ctrl {

	STEDMA40_NO_FLOW_CTRL,

	STEDMA40_FLOW_CTRL,

};



enum stedma40_endianess {

	STEDMA40_LITTLE_ENDIAN,

	STEDMA40_BIG_ENDIAN

};



enum stedma40_periph_data_width {

	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,

	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,

	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,

	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT

};



struct stedma40_half_channel_info {

	enum stedma40_endianess endianess;

	enum stedma40_periph_data_width data_width;

	int psize;

	enum stedma40_flow_ctrl flow_ctrl;

};



enum stedma40_xfer_dir {

	STEDMA40_MEM_TO_MEM,

	STEDMA40_MEM_TO_PERIPH,

	STEDMA40_PERIPH_TO_MEM,

	STEDMA40_PERIPH_TO_PERIPH

};





/**

 * struct stedma40_chan_cfg - Structure to be filled by client drivers.

 *

 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH

 * @channel_type: priority, mode, mode options and interrupt configuration.

 * @src_dev_type: Src device type

 * @dst_dev_type: Dst device type

 * @src_info: Parameters for dst half channel

 * @dst_info: Parameters for dst half channel

 * @pre_transfer_data: Data to be passed on to the pre_transfer() function.

 * @pre_transfer: Callback used if needed before preparation of transfer.

 * Only called if device is set. size of bytes to transfer

 * (in case of multiple element transfer size is size of the first element).

 *

 *

 * This structure has to be filled by the client drivers.

 * It is recommended to do all dma configurations for clients in the machine.

 *

 */

struct stedma40_chan_cfg {

	enum stedma40_xfer_dir			 dir;

	unsigned int				 channel_type;

	int					 src_dev_type;

	int					 dst_dev_type;

	struct stedma40_half_channel_info	 src_info;

	struct stedma40_half_channel_info	 dst_info;

	void					*pre_transfer_data;

	int (*pre_transfer)			(struct dma_chan *chan,

						 void *data,

						 int size);

};



/**

 * struct stedma40_platform_data - Configuration struct for the dma device.

 *

 * @dev_len: length of dev_tx and dev_rx

 * @dev_tx: mapping between destination event line and io address

 * @dev_rx: mapping between source event line and io address

 * @memcpy: list of memcpy event lines

 * @memcpy_len: length of memcpy

 * @memcpy_conf_phy: default configuration of physical channel memcpy

 * @memcpy_conf_log: default configuration of logical channel memcpy

 * @llis_per_log: number of max linked list items per logical channel

 *

 */

struct stedma40_platform_data {

	u32				 dev_len;

	const dma_addr_t		*dev_tx;

	const dma_addr_t		*dev_rx;

	int				*memcpy;

	u32				 memcpy_len;

	struct stedma40_chan_cfg	*memcpy_conf_phy;

	struct stedma40_chan_cfg	*memcpy_conf_log;

	unsigned int			 llis_per_log;

};



/**

 * setdma40_set_psize() - Used for changing the package size of an

 * already configured dma channel.

 *

 * @chan: dmaengine handle

 * @src_psize: new package side for src. (STEDMA40_PSIZE*)

 * @src_psize: new package side for dst. (STEDMA40_PSIZE*)

 *

 * returns 0 on ok, otherwise negative error number.

 */

int stedma40_set_psize(struct dma_chan *chan,

		       int src_psize,

		       int dst_psize);



/**

 * stedma40_filter() - Provides stedma40_chan_cfg to the

 * ste_dma40 dma driver via the dmaengine framework.

 * does some checking of what's provided.

 *

 * Never directly called by client. It used by dmaengine.

 * @chan: dmaengine handle.

 * @data: Must be of type: struct stedma40_chan_cfg and is

 * the configuration of the framework.

 *

 *

 */



bool stedma40_filter(struct dma_chan *chan, void *data);



/**

 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from

 * scattergatter lists.

 *

 * @chan: dmaengine handle

 * @sgl_dst: Destination scatter list

 * @sgl_src: Source scatter list

 * @sgl_len: The length of each scatterlist. Both lists must be of equal length

 * and each element must match the corresponding element in the other scatter

 * list.

 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h

 */



struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,

						   struct scatterlist *sgl_dst,

						   struct scatterlist *sgl_src,

						   unsigned int sgl_len,

						   unsigned long flags);



/**

 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave

 * (=device)

 *

 * @chan: dmaengine handle

 * @addr: source or destination physicall address.

 * @size: bytes to transfer

 * @direction: direction of transfer

 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h

 */



static inline struct

dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,

					    dma_addr_t addr,

					    unsigned int size,

					    enum dma_data_direction direction,

					    unsigned long flags)

{

	struct scatterlist sg;

	sg_init_table(&sg, 1);

	sg.dma_address = addr;

	sg.length = size;



	return chan->device->device_prep_slave_sg(chan, &sg, 1,

						  direction, flags);

}



#endif

crypto/async_tx/async_tx.c

+19 −27
Original line number Diff line number Diff line
@@ -81,18 +81,13 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, 
	struct dma_device *device = chan->device;

	struct dma_async_tx_descriptor *intr_tx = (void *) ~0;



	#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH

	BUG();

	#endif



	/* first check to see if we can still append to depend_tx */

	spin_lock_bh(&depend_tx->lock);

	if (depend_tx->parent && depend_tx->chan == tx->chan) {

		tx->parent = depend_tx;

		depend_tx->next = tx;

	txd_lock(depend_tx);

	if (txd_parent(depend_tx) && depend_tx->chan == tx->chan) {

		txd_chain(depend_tx, tx);

		intr_tx = NULL;

	}

	spin_unlock_bh(&depend_tx->lock);

	txd_unlock(depend_tx);



	/* attached dependency, flush the parent channel */

	if (!intr_tx) {
@@ -111,24 +106,22 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, 
	if (intr_tx) {

		intr_tx->callback = NULL;

		intr_tx->callback_param = NULL;

		tx->parent = intr_tx;

		/* safe to set ->next outside the lock since we know we are

		/* safe to chain outside the lock since we know we are

		 * not submitted yet

		 */

		intr_tx->next = tx;

		txd_chain(intr_tx, tx);



		/* check if we need to append */

		spin_lock_bh(&depend_tx->lock);

		if (depend_tx->parent) {

			intr_tx->parent = depend_tx;

			depend_tx->next = intr_tx;

		txd_lock(depend_tx);

		if (txd_parent(depend_tx)) {

			txd_chain(depend_tx, intr_tx);

			async_tx_ack(intr_tx);

			intr_tx = NULL;

		}

		spin_unlock_bh(&depend_tx->lock);

		txd_unlock(depend_tx);



		if (intr_tx) {

			intr_tx->parent = NULL;

			txd_clear_parent(intr_tx);

			intr_tx->tx_submit(intr_tx);

			async_tx_ack(intr_tx);

		}
@@ -176,21 +169,20 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, 
		 * 2/ dependencies are 1:1 i.e. two transactions can

		 * not depend on the same parent

		 */

		BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||

		       tx->parent);

		BUG_ON(async_tx_test_ack(depend_tx) || txd_next(depend_tx) ||

		       txd_parent(tx));



		/* the lock prevents async_tx_run_dependencies from missing

		 * the setting of ->next when ->parent != NULL

		 */

		spin_lock_bh(&depend_tx->lock);

		if (depend_tx->parent) {

		txd_lock(depend_tx);

		if (txd_parent(depend_tx)) {

			/* we have a parent so we can not submit directly

			 * if we are staying on the same channel: append

			 * else: channel switch

			 */

			if (depend_tx->chan == chan) {

				tx->parent = depend_tx;

				depend_tx->next = tx;

				txd_chain(depend_tx, tx);

				s = ASYNC_TX_SUBMITTED;

			} else

				s = ASYNC_TX_CHANNEL_SWITCH;
@@ -203,7 +195,7 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, 
			else

				s = ASYNC_TX_CHANNEL_SWITCH;

		}

		spin_unlock_bh(&depend_tx->lock);

		txd_unlock(depend_tx);



		switch (s) {

		case ASYNC_TX_SUBMITTED:
@@ -212,12 +204,12 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, 
			async_tx_channel_switch(depend_tx, tx);

			break;

		case ASYNC_TX_DIRECT_SUBMIT:

			tx->parent = NULL;

			txd_clear_parent(tx);

			tx->tx_submit(tx);

			break;

		}

	} else {

		tx->parent = NULL;

		txd_clear_parent(tx);

		tx->tx_submit(tx);

	}

drivers/dma/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -141,6 +141,13 @@ config COH901318 
	help

	  Enable support for ST-Ericsson COH 901 318 DMA.



config STE_DMA40

	bool "ST-Ericsson DMA40 support"

	depends on ARCH_U8500

	select DMA_ENGINE

	help

	  Support for ST-Ericsson DMA40 controller



config AMCC_PPC440SPE_ADMA

	tristate "AMCC PPC440SPe ADMA support"

	depends on 440SPe || 440SP
@@ -149,6 +156,13 @@ config AMCC_PPC440SPE_ADMA 
	help

	  Enable support for the AMCC PPC440SPe RAID engines.



config TIMB_DMA

	tristate "Timberdale FPGA DMA support"

	depends on MFD_TIMBERDALE || HAS_IOMEM

	select DMA_ENGINE

	help

	  Enable support for the Timberdale FPGA DMA engine.



config ARCH_HAS_ASYNC_TX_FIND_CHANNEL

	bool

drivers/dma/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -20,3 +20,5 @@ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o 
obj-$(CONFIG_SH_DMAE) += shdma.o

obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o

obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/

obj-$(CONFIG_TIMB_DMA) += timb_dma.o

obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o

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