Commit 6f4194c8 authored by Matt Atwood's avatar Matt Atwood Committed by Matt Roper
Browse files

drm/i915: add Wa_14010594013: icl,ehl 



The bspec tells us we need to set this bit to avoid potential underruns.

v2: use new register write convention (Anshuman) add bspec 7386 ref.

Bspec: 7386
Bspec: 33450
Bspec: 33451

Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200114041128.11211-1-matthew.s.atwood@intel.com
parent 9c92aa48

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -7769,6 +7769,7 @@ enum { 


#define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)

#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)

#define   CNL_DELAY_PMRSP		(1 << 22)

#define   MASK_WAKEMEM			(1 << 13)

#define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -6643,6 +6643,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) 
	/* Wa_1407352427:icl,ehl */

	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,

			 0, PSDUNIT_CLKGATE_DIS);



	/*Wa_14010594013:icl, ehl */

	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,

			 0, CNL_DELAY_PMRSP);

}



static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)

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