Commit 6f059c64 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/display: Fix Null point error if smu ip was disabled 



from AI, SMU Ip is not indispensable to driver and can be
disabled by user via module parameter ip_block_mask.
so the pp_handle may be NULL.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 355c8db1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+11 −5
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ bool dm_pp_apply_display_requirements( 
			adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;

		}



		if (adev->powerplay.pp_funcs->display_configuration_change)

		if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_configuration_change)

			adev->powerplay.pp_funcs->display_configuration_change(

				adev->powerplay.pp_handle,

				&adev->pm.pm_display_cfg);
@@ -304,7 +304,7 @@ bool dm_pp_get_clock_levels_by_type( 
	struct amd_pp_simple_clock_info validation_clks = { 0 };

	uint32_t i;



	if (adev->powerplay.pp_funcs->get_clock_by_type) {

	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {

		if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,

			dc_to_pp_clock_type(clk_type), &pp_clks)) {

		/* Error in pplib. Provide default values. */
@@ -315,7 +315,7 @@ bool dm_pp_get_clock_levels_by_type( 


	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);



	if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {

	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {

		if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(

						pp_handle, &validation_clks)) {

			/* Error in pplib. Provide default values. */
@@ -398,6 +398,9 @@ bool dm_pp_get_clock_levels_by_type_with_voltage( 
	struct pp_clock_levels_with_voltage pp_clk_info = {0};

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;



	if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)

		return false;



	if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,

						     dc_to_pp_clock_type(clk_type),

						     &pp_clk_info))
@@ -438,7 +441,7 @@ bool dm_pp_apply_clock_for_voltage_request( 
	if (!pp_clock_request.clock_type)

		return false;



	if (adev->powerplay.pp_funcs->display_clock_voltage_request)

	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_clock_voltage_request)

		ret = adev->powerplay.pp_funcs->display_clock_voltage_request(

			adev->powerplay.pp_handle,

			&pp_clock_request);
@@ -455,7 +458,7 @@ bool dm_pp_get_static_clocks( 
	struct amd_pp_clock_info pp_clk_info = {0};

	int ret = 0;



	if (adev->powerplay.pp_funcs->get_current_clocks)

	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_current_clocks)

		ret = adev->powerplay.pp_funcs->get_current_clocks(

			adev->powerplay.pp_handle,

			&pp_clk_info);
@@ -505,6 +508,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp, 
	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;

	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;



	if (!pp_funcs || !pp_funcs->set_watermarks_for_clocks_ranges)

		return;



	for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {

		if (ranges->reader_wm_sets[i].wm_inst > 3)

			wm_dce_clocks[i].wm_set_id = WM_SET_A;

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