Unverified Commit 6eefaee4 authored Apr 27, 2020 by Evan Green Committed by Mark Brown Apr 30, 2020

spi: pxa2xx: Apply CS clk quirk to BXT



With a couple allies at Intel, and much badgering, I got confirmation
from Intel that at least BXT suffers from the same SPI chip-select
issue as Cannonlake (and beyond). The issue being that after going
through runtime suspend/resume, toggling the chip-select line without
also sending data does nothing.

Add the quirk to BXT to briefly toggle dynamic clock gating off and
on, forcing the fabric to wake up enough to notice the CS register
change.

Signed-off-by: Evan Green <evgreen@chromium.org>
Cc: Shobhit Srivastava <shobhit.srivastava@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid


Signed-off-by: Mark Brown <broonie@kernel.org>

parent be6ef160

drivers/spi/spi-pxa2xx.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -150,6 +150,7 @@ static const struct lpss_config lpss_platforms[] = {
		.tx_threshold_hi = 48,
		.cs_sel_shift = 8,
		.cs_sel_mask = 3 << 8,
		.cs_clk_stays_gated = true,
		},
		{ /* LPSS_CNL_SSP */
		.offset = 0x200,

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