of/documentation: update with clock information for exynos hdmi subsystem

	a) phandle of the gpio controller node.

	b) pin number within the gpio controller.

	c) optional flags and pull up/down.

- clocks: list of clock IDs from SoC clock driver.

	a) hdmi: Gate of HDMI IP bus clock.

	b) sclk_hdmi: Gate of HDMI special clock.

	c) sclk_pixel: Pixel special clock, one of the two possible inputs of

		HDMI clock mux.

	d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of

		HDMI clock mux.

	e) mout_hdmi: It is required by the driver to switch between the 2

		parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable

		after configuration, parent is set to sclk_hdmiphy else

		sclk_pixel.

- clock-names: aliases as per driver requirements for above clock IDs:

	"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".

Example:

	hdmi {

- reg: physical base address of the mixer and length of memory mapped

	region.

- interrupts: interrupt number to the cpu.

- clocks: list of clock IDs from SoC clock driver.

	a) mixer: Gate of Mixer IP bus clock.

	b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of

               mixer mux.

Example: