Commit 6edc3185 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Use alternative scratch registers in DTLB miss handler 



In preparation of handling CONFIG_VMAP_STACK, DTLB miss handler need
to use different scratch registers than other exception handlers in
order to not jeopardise exception entry on stack DTLB misses.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c5287ea59ae9630f505019b309bf94029241635f.1576916812.git.christophe.leroy@c-s.fr
parent 547db12f

arch/powerpc/kernel/head_8xx.S

+14 −13
Original line number Diff line number Diff line
@@ -193,8 +193,9 @@ SystemCall: 
0:	lwz	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	addi	r10, r10, 1

	stw	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

#endif
@@ -337,8 +338,8 @@ ITLBMissLinear: 


	. = 0x1200

DataStoreTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10

	mtspr	SPRN_SPRG_SCRATCH1, r11

	mtspr	SPRN_DAR, r10

	mtspr	SPRN_M_TW, r11

	mfcr	r11



	/* If we are faulting a kernel address, we have to use the
@@ -403,10 +404,10 @@ DataStoreTLBMiss: 
	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	/* Restore registers */

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

0:	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

	patch_site	0b, patch__dtlbmiss_exit_1
@@ -422,10 +423,10 @@ DTLBMissIMMR: 
	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

0:	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

	patch_site	0b, patch__dtlbmiss_exit_2
@@ -459,10 +460,10 @@ DTLBMissLinear: 
	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

0:	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

	patch_site	0b, patch__dtlbmiss_exit_3

arch/powerpc/perf/8xx-pmu.c

+8 −4
Original line number Diff line number Diff line
@@ -157,10 +157,6 @@ static void mpc8xx_pmu_read(struct perf_event *event) 


static void mpc8xx_pmu_del(struct perf_event *event, int flags)

{

	/* mfspr r10, SPRN_SPRG_SCRATCH0 */

	unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) |

			    __PPC_SPR(SPRN_SPRG_SCRATCH0);



	mpc8xx_pmu_read(event);



	/* If it was the last user, stop counting to avoid useles overhead */
@@ -173,6 +169,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) 
		break;

	case PERF_8xx_ID_ITLB_LOAD_MISS:

		if (atomic_dec_return(&itlb_miss_ref) == 0) {

			/* mfspr r10, SPRN_SPRG_SCRATCH0 */

			unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) |

					    __PPC_SPR(SPRN_SPRG_SCRATCH0);



			patch_instruction_site(&patch__itlbmiss_exit_1, insn);

#ifndef CONFIG_PIN_TLB_TEXT

			patch_instruction_site(&patch__itlbmiss_exit_2, insn);
@@ -181,6 +181,10 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) 
		break;

	case PERF_8xx_ID_DTLB_LOAD_MISS:

		if (atomic_dec_return(&dtlb_miss_ref) == 0) {

			/* mfspr r10, SPRN_DAR */

			unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) |

					    __PPC_SPR(SPRN_DAR);



			patch_instruction_site(&patch__dtlbmiss_exit_1, insn);

			patch_instruction_site(&patch__dtlbmiss_exit_2, insn);

			patch_instruction_site(&patch__dtlbmiss_exit_3, insn);

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