Commit 6ed83942 authored by Graf Yang's avatar Graf Yang Committed by Bryan Wu
Browse files

[Blackfin] arch: Resolve the clash issue of UART defines between blackfin... 


[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Cc: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent db68254f

arch/blackfin/kernel/bfin_gpio.c

+8 −8
Original line number Diff line number Diff line
@@ -95,14 +95,14 @@ enum { 
	AWA_data_clear = SYSCR,

	AWA_data_set = SYSCR,

	AWA_toggle = SYSCR,

	AWA_maska = UART_SCR,

	AWA_maska_clear = UART_SCR,

	AWA_maska_set = UART_SCR,

	AWA_maska_toggle = UART_SCR,

	AWA_maskb = UART_GCTL,

	AWA_maskb_clear = UART_GCTL,

	AWA_maskb_set = UART_GCTL,

	AWA_maskb_toggle = UART_GCTL,

	AWA_maska = BFIN_UART_SCR,

	AWA_maska_clear = BFIN_UART_SCR,

	AWA_maska_set = BFIN_UART_SCR,

	AWA_maska_toggle = BFIN_UART_SCR,

	AWA_maskb = BFIN_UART_GCTL,

	AWA_maskb_clear = BFIN_UART_GCTL,

	AWA_maskb_set = BFIN_UART_GCTL,

	AWA_maskb_toggle = BFIN_UART_GCTL,

	AWA_dir = SPORT1_STAT,

	AWA_polar = SPORT1_STAT,

	AWA_edge = SPORT1_STAT,

arch/blackfin/mach-bf533/head.S

+8 −8
Original line number Diff line number Diff line
@@ -151,26 +151,26 @@ ENTRY(__start) 


	/* Initialise UART - when booting from u-boot, the UART is not disabled

	 * so if we dont initalize here, our serial console gets hosed */

	p0.h = hi(UART_LCR);

	p0.l = lo(UART_LCR);

	p0.h = hi(BFIN_UART_LCR);

	p0.l = lo(BFIN_UART_LCR);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable DLL writes */

	ssync;



	p0.h = hi(UART_DLL);

	p0.l = lo(UART_DLL);

	p0.h = hi(BFIN_UART_DLL);

	p0.l = lo(BFIN_UART_DLL);

	r0 = 0x0(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_DLH);

	p0.l = lo(UART_DLH);

	p0.h = hi(BFIN_UART_DLH);

	p0.l = lo(BFIN_UART_DLH);

	r0 = 0x00(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_GCTL);

	p0.l = lo(UART_GCTL);

	p0.h = hi(BFIN_UART_GCTL);

	p0.l = lo(BFIN_UART_GCTL);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable UART clock */

	ssync;

arch/blackfin/mach-bf537/head.S

+8 −8
Original line number Diff line number Diff line
@@ -182,26 +182,26 @@ ENTRY(__start) 


	/* Initialise UART - when booting from u-boot, the UART is not disabled

	 * so if we dont initalize here, our serial console gets hosed */

	p0.h = hi(UART_LCR);

	p0.l = lo(UART_LCR);

	p0.h = hi(BFIN_UART_LCR);

	p0.l = lo(BFIN_UART_LCR);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable DLL writes */

	ssync;



	p0.h = hi(UART_DLL);

	p0.l = lo(UART_DLL);

	p0.h = hi(BFIN_UART_DLL);

	p0.l = lo(BFIN_UART_DLL);

	r0 = 0x0(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_DLH);

	p0.l = lo(UART_DLH);

	p0.h = hi(BFIN_UART_DLH);

	p0.l = lo(BFIN_UART_DLH);

	r0 = 0x00(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_GCTL);

	p0.l = lo(UART_GCTL);

	p0.h = hi(BFIN_UART_GCTL);

	p0.l = lo(BFIN_UART_GCTL);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable UART clock */

	ssync;

arch/blackfin/mach-bf561/head.S

+8 −8
Original line number Diff line number Diff line
@@ -139,26 +139,26 @@ ENTRY(__start) 


	/* Initialise UART - when booting from u-boot, the UART is not disabled

	 * so if we dont initalize here, our serial console gets hosed */

	p0.h = hi(UART_LCR);

	p0.l = lo(UART_LCR);

	p0.h = hi(BFIN_UART_LCR);

	p0.l = lo(BFIN_UART_LCR);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable DLL writes */

	ssync;



	p0.h = hi(UART_DLL);

	p0.l = lo(UART_DLL);

	p0.h = hi(BFIN_UART_DLL);

	p0.l = lo(BFIN_UART_DLL);

	r0 = 0x0(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_DLH);

	p0.l = lo(UART_DLH);

	p0.h = hi(BFIN_UART_DLH);

	p0.l = lo(BFIN_UART_DLH);

	r0 = 0x00(Z);

	w[p0] = r0.L;

	ssync;



	p0.h = hi(UART_GCTL);

	p0.l = lo(UART_GCTL);

	p0.h = hi(BFIN_UART_GCTL);

	p0.l = lo(BFIN_UART_GCTL);

	r0 = 0x0(Z);

	w[p0] = r0.L;	/* To enable UART clock */

	ssync;

include/asm-blackfin/mach-bf533/defBF532.h

+17 −12
Original line number Diff line number Diff line
@@ -88,20 +88,25 @@ 
#define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Register (alternate macro) */



/* UART Controller (0xFFC00400 - 0xFFC004FF) */

#define UART_THR             		 0xFFC00400	/* Transmit Holding register */

#define UART_RBR             		 0xFFC00400	/* Receive Buffer register */

#define UART_DLL              		 0xFFC00400	/* Divisor Latch (Low-Byte) */

#define UART_IER              		 0xFFC00404	/* Interrupt Enable Register */

#define UART_DLH              		 0xFFC00404	/* Divisor Latch (High-Byte) */

#define UART_IIR              		 0xFFC00408	/* Interrupt Identification Register */

#define UART_LCR              		 0xFFC0040C	/* Line Control Register */

#define UART_MCR			 0xFFC00410	/* Modem Control Register */

#define UART_LSR              		 0xFFC00414	/* Line Status Register */



/*

 * Because include/linux/serial_reg.h have defined UART_*,

 * So we define blackfin uart regs to BFIN_UART_*.

 */

#define BFIN_UART_THR			0xFFC00400	/* Transmit Holding register */

#define BFIN_UART_RBR			0xFFC00400	/* Receive Buffer register */

#define BFIN_UART_DLL			0xFFC00400	/* Divisor Latch (Low-Byte) */

#define BFIN_UART_IER			0xFFC00404	/* Interrupt Enable Register */

#define BFIN_UART_DLH			0xFFC00404	/* Divisor Latch (High-Byte) */

#define BFIN_UART_IIR			0xFFC00408	/* Interrupt Identification Register */

#define BFIN_UART_LCR			0xFFC0040C	/* Line Control Register */

#define BFIN_UART_MCR			0xFFC00410	/* Modem Control Register */

#define BFIN_UART_LSR			0xFFC00414	/* Line Status Register */

#if 0

#define UART_MSR            		 0xFFC00418   /* Modem Status Register (UNUSED in ADSP-BF532) */

#define BFIN_UART_MSR			0xFFC00418	/* Modem Status Register (UNUSED in ADSP-BF532) */

#endif

#define UART_SCR              		 0xFFC0041C	/* SCR Scratch Register */

#define UART_GCTL      	      		 0xFFC00424	/* Global Control Register */

#define BFIN_UART_SCR			0xFFC0041C	/* SCR Scratch Register */

#define BFIN_UART_GCTL			0xFFC00424	/* Global Control Register */



/* SPI Controller (0xFFC00500 - 0xFFC005FF) */

#define SPI0_REGBASE          		0xFFC00500

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