Commit 6ed30c89 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: addi_apci_3120: prefer using the BIT macro 



As suggested by checkpatch.pl, use the BIT macro to define the
register bits.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6cd46d71

drivers/staging/comedi/drivers/addi_apci_3120.c

+28 −26
Original line number Diff line number Diff line
@@ -31,33 +31,33 @@ 
 * PCI BAR 0 register map (devpriv->amcc)

 * see amcc_s5933.h for register and bit defines

 */

#define APCI3120_FIFO_ADVANCE_ON_BYTE_2		(1 << 29)

#define APCI3120_FIFO_ADVANCE_ON_BYTE_2		BIT(29)



/*

 * PCI BAR 1 register map (dev->iobase)

 */

#define APCI3120_AI_FIFO_REG			0x00

#define APCI3120_CTRL_REG			0x00

#define APCI3120_CTRL_EXT_TRIG			(1 << 15)

#define APCI3120_CTRL_GATE(x)			(1 << (12 + (x)))

#define APCI3120_CTRL_EXT_TRIG			BIT(15)

#define APCI3120_CTRL_GATE(x)			BIT(12 + (x))

#define APCI3120_CTRL_PR(x)			(((x) & 0xf) << 8)

#define APCI3120_CTRL_PA(x)			(((x) & 0xf) << 0)

#define APCI3120_AI_SOFTTRIG_REG		0x02

#define APCI3120_STATUS_REG			0x02

#define APCI3120_STATUS_EOC_INT			(1 << 15)

#define APCI3120_STATUS_AMCC_INT		(1 << 14)

#define APCI3120_STATUS_EOS_INT			(1 << 13)

#define APCI3120_STATUS_TIMER2_INT		(1 << 12)

#define APCI3120_STATUS_EOC_INT			BIT(15)

#define APCI3120_STATUS_AMCC_INT		BIT(14)

#define APCI3120_STATUS_EOS_INT			BIT(13)

#define APCI3120_STATUS_TIMER2_INT		BIT(12)

#define APCI3120_STATUS_INT_MASK		(0xf << 12)

#define APCI3120_STATUS_TO_DI_BITS(x)		(((x) >> 8) & 0xf)

#define APCI3120_STATUS_TO_VERSION(x)		(((x) >> 4) & 0xf)

#define APCI3120_STATUS_FIFO_FULL		(1 << 2)

#define APCI3120_STATUS_FIFO_EMPTY		(1 << 1)

#define APCI3120_STATUS_DA_READY		(1 << 0)

#define APCI3120_STATUS_FIFO_FULL		BIT(2)

#define APCI3120_STATUS_FIFO_EMPTY		BIT(1)

#define APCI3120_STATUS_DA_READY		BIT(0)

#define APCI3120_TIMER_REG			0x04

#define APCI3120_CHANLIST_REG			0x06

#define APCI3120_CHANLIST_INDEX(x)		(((x) & 0xf) << 8)

#define APCI3120_CHANLIST_UNIPOLAR		(1 << 7)

#define APCI3120_CHANLIST_UNIPOLAR		BIT(7)

#define APCI3120_CHANLIST_GAIN(x)		(((x) & 0x3) << 4)

#define APCI3120_CHANLIST_MUX(x)		(((x) & 0xf) << 0)

#define APCI3120_AO_REG(x)			(0x08 + (((x) / 4) * 2))
@@ -74,19 +74,21 @@ 
#define APCI3120_CTR0_DO_BITS(x)		((x) << 4)

#define APCI3120_CTR0_TIMER_SEL(x)		((x) << 0)

#define APCI3120_MODE_REG			0x0e

#define APCI3120_MODE_TIMER2_CLK_OSC		(0 << 6)

#define APCI3120_MODE_TIMER2_CLK_OUT1		(1 << 6)

#define APCI3120_MODE_TIMER2_CLK_EOC		(2 << 6)

#define APCI3120_MODE_TIMER2_CLK_EOS		(3 << 6)

#define APCI3120_MODE_TIMER2_CLK_MASK		(3 << 6)

#define APCI3120_MODE_TIMER2_AS_TIMER		(0 << 4)

#define APCI3120_MODE_TIMER2_AS_COUNTER		(1 << 4)

#define APCI3120_MODE_TIMER2_AS_WDOG		(2 << 4)

#define APCI3120_MODE_TIMER2_AS_MASK		(3 << 4)  /* sets AS_TIMER */

#define APCI3120_MODE_SCAN_ENA			(1 << 3)

#define APCI3120_MODE_TIMER2_IRQ_ENA		(1 << 2)

#define APCI3120_MODE_EOS_IRQ_ENA		(1 << 1)

#define APCI3120_MODE_EOC_IRQ_ENA		(1 << 0)

#define APCI3120_MODE_TIMER2_CLK(x)		(((x) & 0x3) << 6)

#define APCI3120_MODE_TIMER2_CLK_OSC		APCI3120_MODE_TIMER2_CLK(0)

#define APCI3120_MODE_TIMER2_CLK_OUT1		APCI3120_MODE_TIMER2_CLK(1)

#define APCI3120_MODE_TIMER2_CLK_EOC		APCI3120_MODE_TIMER2_CLK(2)

#define APCI3120_MODE_TIMER2_CLK_EOS		APCI3120_MODE_TIMER2_CLK(3)

#define APCI3120_MODE_TIMER2_CLK_MASK		APCI3120_MODE_TIMER2_CLK(3)

#define APCI3120_MODE_TIMER2_AS(x)		(((x) & 0x3) << 4)

#define APCI3120_MODE_TIMER2_AS_TIMER		APCI3120_MODE_TIMER2_AS(0)

#define APCI3120_MODE_TIMER2_AS_COUNTER		APCI3120_MODE_TIMER2_AS(1)

#define APCI3120_MODE_TIMER2_AS_WDOG		APCI3120_MODE_TIMER2_AS(2)

#define APCI3120_MODE_TIMER2_AS_MASK		APCI3120_MODE_TIMER2_AS(3)

#define APCI3120_MODE_SCAN_ENA			BIT(3)

#define APCI3120_MODE_TIMER2_IRQ_ENA		BIT(2)

#define APCI3120_MODE_EOS_IRQ_ENA		BIT(1)

#define APCI3120_MODE_EOC_IRQ_ENA		BIT(0)



/*

 * PCI BAR 2 register map (devpriv->addon)
@@ -94,8 +96,8 @@ 
#define APCI3120_ADDON_ADDR_REG			0x00

#define APCI3120_ADDON_DATA_REG			0x02

#define APCI3120_ADDON_CTRL_REG			0x04

#define APCI3120_ADDON_CTRL_AMWEN_ENA		(1 << 1)

#define APCI3120_ADDON_CTRL_A2P_FIFO_ENA	(1 << 0)

#define APCI3120_ADDON_CTRL_AMWEN_ENA		BIT(1)

#define APCI3120_ADDON_CTRL_A2P_FIFO_ENA	BIT(0)



/*

 * Board revisions

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