tilegx: provide kernel support for the tilegx UART shim (6ec006ed) · Commits · 戴 / test

arch/tile/gxio/Kconfig

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Original line number	Diff line number	Diff line
		@@ -26,3 +26,8 @@ config TILE_GXIO_TRIO
		config TILE_GXIO_USB_HOST
		bool
		select TILE_GXIO

		# Support direct access to the TILE-Gx UART hardware from kernel space.
		config TILE_GXIO_UART
		bool
		select TILE_GXIO

arch/tile/gxio/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -6,4 +6,5 @@ obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
		obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
		obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o
		obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o
		obj-$(CONFIG_TILE_GXIO_UART) += uart.o iorpc_uart.o
		obj-$(CONFIG_TILE_GXIO_USB_HOST) += usb_host.o iorpc_usb_host.o

arch/tile/gxio/iorpc_uart.c

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+77 −0

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		/*
		* Copyright 2013 Tilera Corporation. All Rights Reserved.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation, version 2.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
		* NON INFRINGEMENT. See the GNU General Public License for
		* more details.
		*/

		/* This file is machine-generated; DO NOT EDIT! */
		#include "gxio/iorpc_uart.h"

		struct cfg_interrupt_param {
		union iorpc_interrupt interrupt;
		};

		int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
		int inter_y, int inter_ipi, int inter_event)
		{
		struct cfg_interrupt_param temp;
		struct cfg_interrupt_param *params = &temp;

		params->interrupt.kernel.x = inter_x;
		params->interrupt.kernel.y = inter_y;
		params->interrupt.kernel.ipi = inter_ipi;
		params->interrupt.kernel.event = inter_event;

		return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
		sizeof(*params), GXIO_UART_OP_CFG_INTERRUPT);
		}

		EXPORT_SYMBOL(gxio_uart_cfg_interrupt);

		struct get_mmio_base_param {
		HV_PTE base;
		};

		int gxio_uart_get_mmio_base(gxio_uart_context_t context, HV_PTE base)
		{
		int __result;
		struct get_mmio_base_param temp;
		struct get_mmio_base_param *params = &temp;

		__result =
		hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
		GXIO_UART_OP_GET_MMIO_BASE);
		*base = params->base;

		return __result;
		}

		EXPORT_SYMBOL(gxio_uart_get_mmio_base);

		struct check_mmio_offset_param {
		unsigned long offset;
		unsigned long size;
		};

		int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
		unsigned long offset, unsigned long size)
		{
		struct check_mmio_offset_param temp;
		struct check_mmio_offset_param *params = &temp;

		params->offset = offset;
		params->size = size;

		return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
		sizeof(*params), GXIO_UART_OP_CHECK_MMIO_OFFSET);
		}

		EXPORT_SYMBOL(gxio_uart_check_mmio_offset);

arch/tile/gxio/uart.c

0 → 100644

+87 −0

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		/*
		* Copyright 2013 Tilera Corporation. All Rights Reserved.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation, version 2.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
		* NON INFRINGEMENT. See the GNU General Public License for
		* more details.
		*/

		/*
		* Implementation of UART gxio calls.
		*/

		#include <linux/io.h>
		#include <linux/errno.h>
		#include <linux/module.h>

		#include <gxio/uart.h>
		#include <gxio/iorpc_globals.h>
		#include <gxio/iorpc_uart.h>
		#include <gxio/kiorpc.h>

		int gxio_uart_init(gxio_uart_context_t *context, int uart_index)
		{
		char file[32];
		int fd;

		snprintf(file, sizeof(file), "uart/%d/iorpc", uart_index);
		fd = hv_dev_open((HV_VirtAddr) file, 0);
		if (fd < 0) {
		if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
		return fd;
		else
		return -ENODEV;
		}

		context->fd = fd;

		/* Map in the MMIO space. */
		context->mmio_base = (void __force *)
		iorpc_ioremap(fd, HV_UART_MMIO_OFFSET, HV_UART_MMIO_SIZE);

		if (context->mmio_base == NULL) {
		hv_dev_close(context->fd);
		context->fd = -1;
		return -ENODEV;
		}

		return 0;
		}

		EXPORT_SYMBOL_GPL(gxio_uart_init);

		int gxio_uart_destroy(gxio_uart_context_t *context)
		{
		iounmap((void __force __iomem *)(context->mmio_base));
		hv_dev_close(context->fd);

		context->mmio_base = NULL;
		context->fd = -1;

		return 0;
		}

		EXPORT_SYMBOL_GPL(gxio_uart_destroy);

		/* UART register write wrapper. */
		void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
		uint64_t word)
		{
		__gxio_mmio_write(context->mmio_base + offset, word);
		}

		EXPORT_SYMBOL_GPL(gxio_uart_write);

		/* UART register read wrapper. */
		uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset)
		{
		return __gxio_mmio_read(context->mmio_base + offset);
		}

		EXPORT_SYMBOL_GPL(gxio_uart_read);

arch/tile/include/arch/uart.h

0 → 100644

+300 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2013 Tilera Corporation. All Rights Reserved.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation, version 2.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
		* NON INFRINGEMENT. See the GNU General Public License for
		* more details.
		*/

		/* Machine-generated file; do not edit. */

		#ifndef __ARCH_UART_H__
		#define __ARCH_UART_H__

		#include <arch/abi.h>
		#include <arch/uart_def.h>

		#ifndef __ASSEMBLER__

		/* Divisor. */

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/*
		* Baud Rate Divisor. Desired_baud_rate = REF_CLK frequency / (baud *
		* 16).
		* Note: REF_CLK is always 125 MHz, the default
		* divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
		*/
		uint_reg_t divisor : 12;
		/* Reserved. */
		uint_reg_t __reserved : 52;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved : 52;
		uint_reg_t divisor : 12;
		#endif
		};

		uint_reg_t word;
		} UART_DIVISOR_t;

		/* FIFO Count. */

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/*
		* n: n active entries in the receive FIFO (max is 2**8). Each entry has
		* 8 bits.
		* 0: no active entry in the receive FIFO (that is empty).
		*/
		uint_reg_t rfifo_count : 9;
		/* Reserved. */
		uint_reg_t __reserved_0 : 7;
		/*
		* n: n active entries in the transmit FIFO (max is 2**8). Each entry has
		* 8 bits.
		* 0: no active entry in the transmit FIFO (that is empty).
		*/
		uint_reg_t tfifo_count : 9;
		/* Reserved. */
		uint_reg_t __reserved_1 : 7;
		/*
		* n: n active entries in the write FIFO (max is 2**2). Each entry has 8
		* bits.
		* 0: no active entry in the write FIFO (that is empty).
		*/
		uint_reg_t wfifo_count : 3;
		/* Reserved. */
		uint_reg_t __reserved_2 : 29;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved_2 : 29;
		uint_reg_t wfifo_count : 3;
		uint_reg_t __reserved_1 : 7;
		uint_reg_t tfifo_count : 9;
		uint_reg_t __reserved_0 : 7;
		uint_reg_t rfifo_count : 9;
		#endif
		};

		uint_reg_t word;
		} UART_FIFO_COUNT_t;

		/* FLAG. */

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/* Reserved. */
		uint_reg_t __reserved_0 : 1;
		/* 1: receive FIFO is empty */
		uint_reg_t rfifo_empty : 1;
		/* 1: write FIFO is empty. */
		uint_reg_t wfifo_empty : 1;
		/* 1: transmit FIFO is empty. */
		uint_reg_t tfifo_empty : 1;
		/* 1: receive FIFO is full. */
		uint_reg_t rfifo_full : 1;
		/* 1: write FIFO is full. */
		uint_reg_t wfifo_full : 1;
		/* 1: transmit FIFO is full. */
		uint_reg_t tfifo_full : 1;
		/* Reserved. */
		uint_reg_t __reserved_1 : 57;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved_1 : 57;
		uint_reg_t tfifo_full : 1;
		uint_reg_t wfifo_full : 1;
		uint_reg_t rfifo_full : 1;
		uint_reg_t tfifo_empty : 1;
		uint_reg_t wfifo_empty : 1;
		uint_reg_t rfifo_empty : 1;
		uint_reg_t __reserved_0 : 1;
		#endif
		};

		uint_reg_t word;
		} UART_FLAG_t;

		/*
		* Interrupt Vector Mask.
		* Each bit in this register corresponds to a specific interrupt. When set,
		* the associated interrupt will not be dispatched.
		*/

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/* Read data FIFO read and no data available */
		uint_reg_t rdat_err : 1;
		/* Write FIFO was written but it was full */
		uint_reg_t wdat_err : 1;
		/* Stop bit not found when current data was received */
		uint_reg_t frame_err : 1;
		/* Parity error was detected when current data was received */
		uint_reg_t parity_err : 1;
		/* Data was received but the receive FIFO was full */
		uint_reg_t rfifo_overflow : 1;
		/*
		* An almost full event is reached when data is to be written to the
		* receive FIFO, and the receive FIFO has more than or equal to
		* BUFFER_THRESHOLD.RFIFO_AFULL bytes.
		*/
		uint_reg_t rfifo_afull : 1;
		/* Reserved. */
		uint_reg_t __reserved_0 : 1;
		/* An entry in the transmit FIFO was popped */
		uint_reg_t tfifo_re : 1;
		/* An entry has been pushed into the receive FIFO */
		uint_reg_t rfifo_we : 1;
		/* An entry of the write FIFO has been popped */
		uint_reg_t wfifo_re : 1;
		/* Rshim read receive FIFO in protocol mode */
		uint_reg_t rfifo_err : 1;
		/*
		* An almost empty event is reached when data is to be read from the
		* transmit FIFO, and the transmit FIFO has less than or equal to
		* BUFFER_THRESHOLD.TFIFO_AEMPTY bytes.
		*/
		uint_reg_t tfifo_aempty : 1;
		/* Reserved. */
		uint_reg_t __reserved_1 : 52;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved_1 : 52;
		uint_reg_t tfifo_aempty : 1;
		uint_reg_t rfifo_err : 1;
		uint_reg_t wfifo_re : 1;
		uint_reg_t rfifo_we : 1;
		uint_reg_t tfifo_re : 1;
		uint_reg_t __reserved_0 : 1;
		uint_reg_t rfifo_afull : 1;
		uint_reg_t rfifo_overflow : 1;
		uint_reg_t parity_err : 1;
		uint_reg_t frame_err : 1;
		uint_reg_t wdat_err : 1;
		uint_reg_t rdat_err : 1;
		#endif
		};

		uint_reg_t word;
		} UART_INTERRUPT_MASK_t;

		/*
		* Interrupt vector, write-one-to-clear.
		* Each bit in this register corresponds to a specific interrupt. Hardware
		* sets the bit when the associated condition has occurred. Writing a 1
		* clears the status bit.
		*/

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/* Read data FIFO read and no data available */
		uint_reg_t rdat_err : 1;
		/* Write FIFO was written but it was full */
		uint_reg_t wdat_err : 1;
		/* Stop bit not found when current data was received */
		uint_reg_t frame_err : 1;
		/* Parity error was detected when current data was received */
		uint_reg_t parity_err : 1;
		/* Data was received but the receive FIFO was full */
		uint_reg_t rfifo_overflow : 1;
		/*
		* Data was received and the receive FIFO is now almost full (more than
		* BUFFER_THRESHOLD.RFIFO_AFULL bytes in it)
		*/
		uint_reg_t rfifo_afull : 1;
		/* Reserved. */
		uint_reg_t __reserved_0 : 1;
		/* An entry in the transmit FIFO was popped */
		uint_reg_t tfifo_re : 1;
		/* An entry has been pushed into the receive FIFO */
		uint_reg_t rfifo_we : 1;
		/* An entry of the write FIFO has been popped */
		uint_reg_t wfifo_re : 1;
		/* Rshim read receive FIFO in protocol mode */
		uint_reg_t rfifo_err : 1;
		/*
		* Data was read from the transmit FIFO and now it is almost empty (less
		* than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it).
		*/
		uint_reg_t tfifo_aempty : 1;
		/* Reserved. */
		uint_reg_t __reserved_1 : 52;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved_1 : 52;
		uint_reg_t tfifo_aempty : 1;
		uint_reg_t rfifo_err : 1;
		uint_reg_t wfifo_re : 1;
		uint_reg_t rfifo_we : 1;
		uint_reg_t tfifo_re : 1;
		uint_reg_t __reserved_0 : 1;
		uint_reg_t rfifo_afull : 1;
		uint_reg_t rfifo_overflow : 1;
		uint_reg_t parity_err : 1;
		uint_reg_t frame_err : 1;
		uint_reg_t wdat_err : 1;
		uint_reg_t rdat_err : 1;
		#endif
		};

		uint_reg_t word;
		} UART_INTERRUPT_STATUS_t;

		/* Type. */

		__extension__
		typedef union
		{
		struct
		{
		#ifndef __BIG_ENDIAN__
		/* Number of stop bits, rx and tx */
		uint_reg_t sbits : 1;
		/* Reserved. */
		uint_reg_t __reserved_0 : 1;
		/* Data word size, rx and tx */
		uint_reg_t dbits : 1;
		/* Reserved. */
		uint_reg_t __reserved_1 : 1;
		/* Parity selection, rx and tx */
		uint_reg_t ptype : 3;
		/* Reserved. */
		uint_reg_t __reserved_2 : 57;
		#else /* __BIG_ENDIAN__ */
		uint_reg_t __reserved_2 : 57;
		uint_reg_t ptype : 3;
		uint_reg_t __reserved_1 : 1;
		uint_reg_t dbits : 1;
		uint_reg_t __reserved_0 : 1;
		uint_reg_t sbits : 1;
		#endif
		};

		uint_reg_t word;
		} UART_TYPE_t;
		#endif /* !defined(__ASSEMBLER__) */

		#endif /* !defined(__ARCH_UART_H__) */

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