Commit 6eb81373 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-socfpga' into clk-next 

* clk-socfpga:
  clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
  clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
  dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
parents b3a9e3b9 44a7f3e8

drivers/clk/socfpga/clk-agilex.c

+6 −2
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 
	  0, 0, 0, 0, 0x30, 0, 0},

	{ AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,

	  0, 0, 0, 0, 0, 0, 4},

	{ AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24,

	{ AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,

	  0, 0, 0, 0, 0, 0, 2},

	{ AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,

	  1, 0x44, 0, 2, 0, 0, 0},
@@ -294,8 +294,12 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 
	  8, 0, 0, 0, 0, 0, 0},

	{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,

	  9, 0, 0, 0, 0, 0, 0},

	{ AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C,

	{ AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,

	  10, 0, 0, 0, 0, 0, 0},

	{ AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,

	  10, 0, 0, 0, 0, 0, 4},

	{ AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,

	  10, 0, 0, 0, 0, 0, 4},

};



static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,

include/dt-bindings/clock/agilex-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ 
#define AGILEX_SDMMC_CLK		50

#define AGILEX_SPI_M_CLK		51

#define AGILEX_USB_CLK			52

#define AGILEX_NUM_CLKS			53

#define AGILEX_NAND_X_CLK		53

#define AGILEX_NAND_ECC_CLK		54

#define AGILEX_NUM_CLKS			55



#endif	/* __AGILEX_CLOCK_H */

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