iommu/arm-smmu: Set SMTNMB_TLBEN in ACR to enable caching of bypass entries (6eb18d4a) · Commits · 戴 / test

The SMTNMB_TLBEN in the Auxiliary Configuration Register (ACR) provides an option to enable the updation of TLB in case of bypass transactions due to no stream match in the stream match table. This reduces the latencies of the subsequent transactions with the same stream-id which bypasses the SMMU. This provides a significant performance benefit for certain networking workloads. With this change substantial performance improvement of ~9% is observed with DPDK l3fwd application (http://dpdk.org/doc/guides/sample_app_ug/l3_forward.html ) on NXP's LS2088a platform. Reviewed-by:

Robin Murphy <robin.murphy@arm.com> Signed-off-by:

Nipun Gupta <nipun.gupta@nxp.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

drivers/iommu/arm-smmu.c

+16 −9

Original line number	Diff line number	Diff line
		@@ -247,6 +247,7 @@ enum arm_smmu_s2cr_privcfg {
		#define ARM_MMU500_ACTLR_CPRE (1 << 1)

		#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
		#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)

		#define CB_PAR_F (1 << 0)

		@@ -1581,6 +1582,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
		for (i = 0; i < smmu->num_mapping_groups; ++i)
		arm_smmu_write_sme(smmu, i);

		if (smmu->model == ARM_MMU500) {
		/*
		* Before clearing ARM_MMU500_ACTLR_CPRE, need to
		* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
		@@ -1588,9 +1590,14 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
		*/
		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
		major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
		if ((smmu->model == ARM_MMU500) && (major >= 2)) {
		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
		if (major >= 2)
		reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
		/*
		* Allow unmatched Stream IDs to allocate bypass
		* TLB entries for reduced latency.
		*/
		reg \|= ARM_MMU500_ACR_SMTNMB_TLBEN;
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
		}

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