Commit 6eac4027 authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: create and use a common M53xx ColdFire class of CPUs 



The current CONFIG_M532x support definitions are actually common to a larger
set of version 3 ColdFire CPU types. In the future we want to add support for
the 537x family. It is very similar to the 532x internally, and will be able
to use most of the same definitions.

Create a CONFIG_M53xx option that is enabled to support any of the common
532x and 537x CPU types. Convert the current users of CONFIG_M532x to use
CONFIG_M53xx instead.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 0d5340f9

arch/m68k/Kconfig.cpu

+4 −0
Original line number Diff line number Diff line
@@ -224,9 +224,13 @@ config M5307 
	help

	  Motorola ColdFire 5307 processor support.



config M53xx

	bool



config M532x

	bool "MCF532x"

	depends on !MMU

	select M53xx

	select HAVE_CACHE_CB

	help

	  Freescale (Motorola) ColdFire 532x processor support.

arch/m68k/include/asm/dma.h

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#define MAX_M68K_DMA_CHANNELS 4

#elif defined(CONFIG_M5272)

#define MAX_M68K_DMA_CHANNELS 1

#elif defined(CONFIG_M532x)

#elif defined(CONFIG_M53xx)

#define MAX_M68K_DMA_CHANNELS 0

#else

#define MAX_M68K_DMA_CHANNELS 2

arch/m68k/include/asm/m53xxacr.h

+2 −2
Original line number Diff line number Diff line
@@ -55,8 +55,8 @@ 
#define	CACHE_SIZE	0x2000		/* 8k of unified cache */

#define	ICACHE_SIZE	CACHE_SIZE

#define	DCACHE_SIZE	CACHE_SIZE

#elif defined(CONFIG_M532x)

#define	CACHE_SIZE	0x4000		/* 32k of unified cache */

#elif defined(CONFIG_M53xx)

#define	CACHE_SIZE	0x4000		/* 16k of unified cache */

#define	ICACHE_SIZE	CACHE_SIZE

#define	DCACHE_SIZE	CACHE_SIZE

#endif

arch/m68k/include/asm/m532xsim.h→arch/m68k/include/asm/m53xxsim.h

+5 −5
Original line number Diff line number Diff line 
/****************************************************************************/



/*

 *	m532xsim.h -- ColdFire 5329 registers

 *	m53xxsim.h -- ColdFire 5329 registers

 */



/****************************************************************************/

#ifndef	m532xsim_h

#define	m532xsim_h

#ifndef	m53xxsim_h

#define	m53xxsim_h

/****************************************************************************/



#define	CPU_NAME		"COLDFIRE(m532x)"

#define	CPU_NAME		"COLDFIRE(m53xx)"

#define	CPU_INSTR_PER_JIFFY	3

#define	MCF_BUSCLK		(MCF_CLK / 3)
@@ -1238,4 +1238,4 @@ 
#define MCFEPORT_EPFR                 (0xFC094006)



/********************************************************************/

#endif	/* m532xsim_h */
 
#endif	/* m53xxsim_h */

arch/m68k/include/asm/mcfgpio.h

+5 −5
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ static inline void gpio_free(unsigned gpio) 
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \

    defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \

    defined(CONFIG_M5441x)



/* These parts have GPIO organized by 8 bit ports */
@@ -139,7 +139,7 @@ static inline void gpio_free(unsigned gpio) 


#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M532x) || defined(CONFIG_M5441x)

    defined(CONFIG_M53xx) || defined(CONFIG_M5441x)

/*

 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses

 * read-modify-write to change an output and a GPIO module which has separate
@@ -195,7 +195,7 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio) 
		return MCFSIM2_GPIO1READ;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

      defined(CONFIG_M532x) || defined(CONFIG_M5441x)

      defined(CONFIG_M53xx) || defined(CONFIG_M5441x)

#if !defined(CONFIG_M5441x)

	if (gpio < 8)

		return MCFEPORT_EPPDR;
@@ -237,7 +237,7 @@ static inline u32 __mcfgpio_podr(unsigned gpio) 
		return MCFSIM2_GPIO1WRITE;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

      defined(CONFIG_M532x) || defined(CONFIG_M5441x)

      defined(CONFIG_M53xx) || defined(CONFIG_M5441x)

#if !defined(CONFIG_M5441x)

	if (gpio < 8)

		return MCFEPORT_EPDR;
@@ -279,7 +279,7 @@ static inline u32 __mcfgpio_pddr(unsigned gpio) 
		return MCFSIM2_GPIO1ENABLE;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

      defined(CONFIG_M532x) || defined(CONFIG_M5441x)

      defined(CONFIG_M53xx) || defined(CONFIG_M5441x)

#if !defined(CONFIG_M5441x)

	if (gpio < 8)

		return MCFEPORT_EPDDR;

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