Commit 6ea6be77 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-next-2020-09-21' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 



drm-misc-next for 5.10:

UAPI Changes:

Cross-subsystem Changes:
  - virtio: Merged a PR for patches that will affect drm/virtio

Core Changes:
  - dev: More devm_drm convertions and removal of drm_dev_init
  - atomic: Split out drm_atomic_helper_calc_timestamping_constants of
    drm_atomic_helper_update_legacy_modeset_state
  - ttm: More rework

Driver Changes:
  - i915: selftests improvements
  - panfrost: support for Amlogic SoC
  - vc4: one fix
  - tree-wide: conversions to devm_drm_dev_alloc,
  - ast: simplifications of the atomic modesetting code
  - panfrost: multiple fixes
  - vc4: multiple fixes
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921152956.2gxnsdgxmwhvjyut@gilmour.lan
parents fc88fef9 089d8341

Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom BCM2711 HDMI Controller Device Tree Bindings



maintainers:

  - Eric Anholt <eric@anholt.net>



properties:

  compatible:

    enum:

      - brcm,bcm2711-hdmi0

      - brcm,bcm2711-hdmi1



  reg:

    items:

      - description: HDMI controller register range

      - description: DVP register range

      - description: HDMI PHY register range

      - description: Rate Manager register range

      - description: Packet RAM register range

      - description: Metadata RAM register range

      - description: CSC register range

      - description: CEC register range

      - description: HD register range



  reg-names:

    items:

      - const: hdmi

      - const: dvp

      - const: phy

      - const: rm

      - const: packet

      - const: metadata

      - const: csc

      - const: cec

      - const: hd



  clocks:

    items:

      - description: The HDMI state machine clock

      - description: The Pixel BVB clock

      - description: The HDMI Audio parent clock

      - description: The HDMI CEC parent clock



  clock-names:

    items:

      - const: hdmi

      - const: bvb

      - const: audio

      - const: cec



  ddc:

    allOf:

      - $ref: /schemas/types.yaml#/definitions/phandle

    description: >

      Phandle of the I2C controller used for DDC EDID probing



  hpd-gpios:

    description: >

      The GPIO pin for the HDMI hotplug detect (if it doesn't appear

      as an interrupt/status bit in the HDMI controller itself)



  dmas:

    maxItems: 1

    description: >

      Should contain one entry pointing to the DMA channel used to

      transfer audio data.



  dma-names:

    const: audio-rx



  resets:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - resets

  - ddc



additionalProperties: false



examples:

  - |

    hdmi0: hdmi@7ef00700 {

        compatible = "brcm,bcm2711-hdmi0";

        reg = <0x7ef00700 0x300>,

              <0x7ef00300 0x200>,

              <0x7ef00f00 0x80>,

              <0x7ef00f80 0x80>,

              <0x7ef01b00 0x200>,

              <0x7ef01f00 0x400>,

              <0x7ef00200 0x80>,

              <0x7ef04300 0x100>,

              <0x7ef20000 0x100>;

        reg-names = "hdmi",

                    "dvp",

                    "phy",

                    "rm",

                    "packet",

                    "metadata",

                    "csc",

                    "cec",

                    "hd";

        clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;

        clock-names = "hdmi", "bvb", "audio", "cec";

        resets = <&dvp 0>;

        ddc = <&ddc0>;

    };



...

Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml

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@@ -11,7 +11,9 @@ maintainers: 


properties:

  compatible:

    const: brcm,bcm2835-hvs

    enum:

      - brcm,bcm2711-hvs

      - brcm,bcm2835-hvs



  reg:

    maxItems: 1
@@ -19,6 +21,10 @@ properties: 
  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1

    description: Core Clock



required:

  - compatible

  - reg
@@ -26,6 +32,16 @@ required: 


additionalProperties: false



if:

  properties:

    compatible:

      contains:

        const: brcm,bcm2711-hvs"



then:

  required:

    - clocks



examples:

  - |

    hvs@7e400000 {

Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml

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@@ -15,6 +15,11 @@ properties: 
      - brcm,bcm2835-pixelvalve0

      - brcm,bcm2835-pixelvalve1

      - brcm,bcm2835-pixelvalve2

      - brcm,bcm2711-pixelvalve0

      - brcm,bcm2711-pixelvalve1

      - brcm,bcm2711-pixelvalve2

      - brcm,bcm2711-pixelvalve3

      - brcm,bcm2711-pixelvalve4



  reg:

    maxItems: 1

Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml

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@@ -17,6 +17,7 @@ description: > 
properties:

  compatible:

    enum:

      - brcm,bcm2711-vc5

      - brcm,bcm2835-vc4

      - brcm,cygnus-vc4

Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 NXP

%YAML 1.2

---

$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: iMX8MQ Display Controller Subsystem (DCSS)



maintainers:

  - Laurentiu Palcu <laurentiu.palcu@nxp.com>



description:



  The DCSS (display controller sub system) is used to source up to three

  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP

  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10

  image processing capabilities are included to provide a solution capable of

  driving next generation high dynamic range displays.



properties:

  compatible:

    const: nxp,imx8mq-dcss



  reg:

    items:

      - description: DCSS base address and size, up to IRQ steer start

      - description: DCSS BLKCTL base address and size



  interrupts:

    items:

      - description: Context loader completion and error interrupt

      - description: DTG interrupt used to signal context loader trigger time

      - description: DTG interrupt for Vblank



  interrupt-names:

    items:

      - const: ctxld

      - const: ctxld_kick

      - const: vblank



  clocks:

    items:

      - description: Display APB clock for all peripheral PIO access interfaces

      - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL

      - description: RTRAM clock

      - description: Pixel clock, can be driven either by HDMI phy clock or MIPI

      - description: DTRC clock, needed by video decompressor



  clock-names:

    items:

      - const: apb

      - const: axi

      - const: rtrm

      - const: pix

      - const: dtrc



  assigned-clocks:

    items:

      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT

      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM

      - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or

                     IMX8MQ_VIDEO_PLL1_REF_SEL



  assigned-clock-parents:

    items:

      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M

      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M

      - description: Phandle and clock specifier of IMX8MQ_CLK_27M



  assigned-clock-rates:

    items:

      - description: Must be 800 MHz

      - description: Must be 400 MHz



  port:

    type: object

    description:

      A port node pointing to the input port of a HDMI/DP or MIPI display bridge.



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mq-clock.h>

    dcss: display-controller@32e00000 {

        compatible = "nxp,imx8mq-dcss";

        reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;

        interrupts = <6>, <8>, <9>;

        interrupt-names = "ctxld", "ctxld_kick", "vblank";

        interrupt-parent = <&irqsteer>;

        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,

                 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,

                 <&clk IMX8MQ_CLK_DISP_DTRC>;

        clock-names = "apb", "axi", "rtrm", "pix", "dtrc";

        assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,

                          <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;

        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,

                                 <&clk IMX8MQ_CLK_27M>;

        assigned-clock-rates = <800000000>,

                               <400000000>;

        port {

            dcss_out: endpoint {

                remote-endpoint = <&hdmi_in>;

            };

        };

    };

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