Commit 6e7aceeb authored Mar 25, 2013 by Rob Herring Committed by Russell King Apr 03, 2013

ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init



Commit b8db6b88 (ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache
ctrl) moved the masking of the part ID which caused the RTL version to be
lost. Commit 6248d060 (ARM: 7545/1: cache-l2x0: make outer_cache_fns a
field of l2x0_of_data) changed how .set_debug is initialized. Both commits
break commit 74ddcdb8 (ARM: 7608/1: l2x0: Only set .set_debug
on PL310 r3p0 and earlier) which uses the RTL version to conditionally set
.set_debug function pointer. Commit b8db6b88 also caused the printed cache
ID to be missing the version information.

Fix this by reverting how the part number is masked so the RTL version
info is maintained. The cache-id-part DT property does not set the RTL
bits so masking them should have no effect. Also, re-arrange the order
of the function pointer init so the .set_debug function can be overridden.

Reported-by: Paolo Pisati <paolo.pisati@canonical.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 698613b6

arch/arm/mm/cache-l2x0.c

+4 −7

Original line number	Diff line number	Diff line
		@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
		int lockregs;
		int i;

		switch (cache_id) {
		switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
		case L2X0_CACHE_ID_PART_L310:
		lockregs = 8;
		break;
		@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
		if (cache_id_part_number_from_dt)
		cache_id = cache_id_part_number_from_dt;
		else
		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
		& L2X0_CACHE_ID_PART_MASK;
		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
		aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

		aux &= aux_mask;
		aux \|= aux_val;

		/* Determine the number of ways */
		switch (cache_id) {
		switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
		case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
		ways = 16;
		@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
		.flush_all = l2x0_flush_all,
		.inv_all = l2x0_inv_all,
		.disable = l2x0_disable,
		.set_debug = pl310_set_debug,
		},
		};

		@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
		data->save();

		of_init = true;
		l2x0_init(l2x0_base, aux_val, aux_mask);

		memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
		l2x0_init(l2x0_base, aux_val, aux_mask);

		return 0;
		}

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