Commit 6e62a888 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: generic: Support MIPS Boston development boards 



Add support for the MIPS Boston development board to generic kernels,
which essentially amounts to:

  - Adding the device tree source for the MIPS Boston board.

  - Adding a Kconfig fragment which enables the appropriate drivers for
    the MIPS Boston board.

With these changes in place generic kernels will support the board by
default, and kernels with only the drivers needed for Boston enabled can
be configured by setting BOARDS=boston during configuration. For
example:

  $ make ARCH=mips 64r6el_defconfig BOARDS=boston

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16485/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4d2804b7

MAINTAINERS

+2 −0
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@@ -8509,6 +8509,8 @@ M: Paul Burton <paul.burton@imgtec.com> 
L:	linux-mips@linux-mips.org

S:	Maintained

F:	Documentation/devicetree/bindings/clock/img,boston-clock.txt

F:	arch/mips/boot/dts/img/boston.dts

F:	arch/mips/configs/generic/board-boston.config

F:	drivers/clk/imgtec/clk-boston.c

F:	include/dt-bindings/clock/boston-clock.h

arch/mips/boot/dts/img/Makefile

+2 −0
Original line number Diff line number Diff line 
dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON)	+= boston.dtb



dtb-$(CONFIG_MACH_PISTACHIO)	+= pistachio_marduk.dtb

obj-$(CONFIG_MACH_PISTACHIO)	+= pistachio_marduk.dtb.o

arch/mips/boot/dts/img/boston.dts

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+224 −0
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/dts-v1/;



#include <dt-bindings/clock/boston-clock.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/mips-gic.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "img,boston";



	chosen {

		stdout-path = "uart0:115200";

	};



	aliases {

		uart0 = &uart0;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "img,mips";

			reg = <0>;

			clocks = <&clk_boston BOSTON_CLK_CPU>;

		};

	};



	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x10000000>;

	};



	pci0: pci@10000000 {

		compatible = "xlnx,axi-pcie-host-1.00.a";

		device_type = "pci";

		reg = <0x10000000 0x2000000>;



		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;



		ranges = <0x02000000 0 0x40000000

			  0x40000000 0 0x40000000>;



		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pci0_intc 1>,

				<0 0 0 2 &pci0_intc 2>,

				<0 0 0 3 &pci0_intc 3>,

				<0 0 0 4 &pci0_intc 4>;



		pci0_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



	pci1: pci@12000000 {

		compatible = "xlnx,axi-pcie-host-1.00.a";

		device_type = "pci";

		reg = <0x12000000 0x2000000>;



		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;



		ranges = <0x02000000 0 0x20000000

			  0x20000000 0 0x20000000>;



		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pci1_intc 1>,

				<0 0 0 2 &pci1_intc 2>,

				<0 0 0 3 &pci1_intc 3>,

				<0 0 0 4 &pci1_intc 4>;



		pci1_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



	pci2: pci@14000000 {

		compatible = "xlnx,axi-pcie-host-1.00.a";

		device_type = "pci";

		reg = <0x14000000 0x2000000>;



		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;



		ranges = <0x02000000 0 0x16000000

			  0x16000000 0 0x100000>;



		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pci2_intc 1>,

				<0 0 0 2 &pci2_intc 2>,

				<0 0 0 3 &pci2_intc 3>,

				<0 0 0 4 &pci2_intc 4>;



		pci2_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};



		pci2_root@0,0,0 {

			compatible = "pci10ee,7021";

			reg = <0x00000000 0 0 0 0>;



			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;



			eg20t_bridge@1,0,0 {

				compatible = "pci8086,8800";

				reg = <0x00010000 0 0 0 0>;



				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;



				eg20t_mac@2,0,1 {

					compatible = "pci8086,8802";

					reg = <0x00020100 0 0 0 0>;

					phy-reset-gpios = <&eg20t_gpio 6

							   GPIO_ACTIVE_LOW>;

				};



				eg20t_gpio: eg20t_gpio@2,0,2 {

					compatible = "pci8086,8803";

					reg = <0x00020200 0 0 0 0>;



					gpio-controller;

					#gpio-cells = <2>;

				};



				eg20t_i2c@2,12,2 {

					compatible = "pci8086,8817";

					reg = <0x00026200 0 0 0 0>;



					#address-cells = <1>;

					#size-cells = <0>;



					rtc@0x68 {

						compatible = "st,m41t81s";

						reg = <0x68>;

					};

				};

			};

		};

	};



	gic: interrupt-controller@16120000 {

		compatible = "mti,gic";

		reg = <0x16120000 0x20000>;



		interrupt-controller;

		#interrupt-cells = <3>;



		timer {

			compatible = "mti,gic-timer";

			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

			clocks = <&clk_boston BOSTON_CLK_CPU>;

		};

	};



	cdmm@16140000 {

		compatible = "mti,mips-cdmm";

		reg = <0x16140000 0x8000>;

	};



	cpc@16200000 {

		compatible = "mti,mips-cpc";

		reg = <0x16200000 0x8000>;

	};



	plat_regs: system-controller@17ffd000 {

		compatible = "img,boston-platform-regs", "syscon";

		reg = <0x17ffd000 0x1000>;



		clk_boston: clock {

			compatible = "img,boston-clock";

			#clock-cells = <1>;

		};

	};



	reboot: syscon-reboot {

		compatible = "syscon-reboot";

		regmap = <&plat_regs>;

		offset = <0x10>;

		mask = <0x10>;

	};



	uart0: uart@17ffe000 {

		compatible = "ns16550a";

		reg = <0x17ffe000 0x1000>;

		reg-shift = <2>;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&clk_boston BOSTON_CLK_SYS>;

	};



	lcd: lcd@17fff000 {

		compatible = "img,boston-lcd";

		reg = <0x17fff000 0x8>;

	};

};

arch/mips/configs/generic/board-boston.config

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CONFIG_FIT_IMAGE_FDT_BOSTON=y



CONFIG_ATA=y

CONFIG_SATA_AHCI=y

CONFIG_SCSI=y

CONFIG_BLK_DEV_SD=y



CONFIG_AUXDISPLAY=y

CONFIG_IMG_ASCII_LCD=y



CONFIG_COMMON_CLK_BOSTON=y



CONFIG_DMADEVICES=y

CONFIG_PCH_DMA=y



CONFIG_GPIOLIB=y

CONFIG_GPIO_SYSFS=y

CONFIG_GPIO_PCH=y



CONFIG_I2C=y

CONFIG_I2C_EG20T=y



CONFIG_MMC=y

CONFIG_MMC_SDHCI=y

CONFIG_MMC_SDHCI_PCI=y



CONFIG_NETDEVICES=y

CONFIG_PCH_GBE=y



CONFIG_PCI=y

CONFIG_PCI_MSI=y

CONFIG_PCIE_XILINX=y



CONFIG_PCH_PHUB=y



CONFIG_RTC_CLASS=y

CONFIG_RTC_DRV_M41T80=y



CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_SERIAL_OF_PLATFORM=y



CONFIG_SPI=y

CONFIG_SPI_TOPCLIFF_PCH=y



CONFIG_USB=y

CONFIG_USB_EHCI_HCD=y

CONFIG_USB_OHCI_HCD=y

arch/mips/generic/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ config YAMON_DT_SHIM 
	  and you wish to include code which helps translate various

	  YAMON-provided environment variables into a device tree properties.



comment "Legacy (non-UHI/non-FIT) Boards"



config LEGACY_BOARD_SEAD3

	bool "Support MIPS SEAD-3 boards"

	select LEGACY_BOARDS
@@ -24,4 +26,14 @@ config LEGACY_BOARD_SEAD3 
	  Enable this to include support for booting on MIPS SEAD-3 FPGA-based

	  development boards, which boot using a legacy boot protocol.



comment "FIT/UHI Boards"



config FIT_IMAGE_FDT_BOSTON

	bool "Include FDT for MIPS Boston boards"

	help

	  Enable this to include the FDT for the MIPS Boston development board

	  from Imagination Technologies in the FIT kernel image. You should

	  enable this if you wish to boot on a MIPS Boston board, as it is

	  expected by the bootloader.



endif

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