drm/dp: add subheadings to DPCD address definitions

#define DP_AUX_I2C_REPLY_DEFER		(0x2 << 2)

#define DP_AUX_I2C_REPLY_MASK		(0x3 << 2)

/* AUX CH addresses */

/* DPCD */

/* DPCD Field Address Mapping */

/* Receiver Capability */

#define DP_DPCD_REV                         0x000

# define DP_DPCD_REV_10                     0x10

# define DP_DPCD_REV_11                     0x11

#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1

#define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2

/* link configuration */

/* Link Configuration */

#define	DP_LINK_BW_SET		            0x100

# define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */

# define DP_LINK_BW_1_62		    0x06

#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1

#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

/* Link/Sink Device Status */

#define DP_SINK_COUNT			    0x200

/* prior to 1.2 bit 7 was reserved mbz */

# define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))

#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */

/* up to ID_SLOT_63 at 0x2ff */

/* Source Device-specific */

#define DP_SOURCE_OUI			    0x300

/* Sink Device-specific */

#define DP_SINK_OUI			    0x400

/* Branch Device-specific */

#define DP_BRANCH_OUI			    0x500

#define DP_BRANCH_ID                        0x503

#define DP_BRANCH_REVISION_START            0x509

#define DP_BRANCH_HW_REV                    0x509

#define DP_BRANCH_SW_REV                    0x50A

/* Link/Sink Device Power Control */

#define DP_SET_POWER                        0x600

# define DP_SET_POWER_D0                    0x1

# define DP_SET_POWER_D3                    0x2

# define DP_SET_POWER_MASK                  0x3

# define DP_SET_POWER_D3_AUX_ON             0x5

/* eDP-specific */

#define DP_EDP_DPCD_REV			    0x700    /* eDP 1.2 */

# define DP_EDP_11			    0x00

# define DP_EDP_12			    0x01

#define DP_EDP_REGIONAL_BACKLIGHT_BASE      0x740    /* eDP 1.4 */

#define DP_EDP_REGIONAL_BACKLIGHT_0	    0x741    /* eDP 1.4 */

/* Sideband MSG Buffers */

#define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */

#define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */

#define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */

#define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */

/* DPRX Event Status Indicator */

#define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */

/* 0-5 sink count */

# define DP_SINK_COUNT_CP_READY             (1 << 6)

#define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same as 0x204 */

#define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */

/* Extended Receiver Capability */

#define DP_DP13_DPCD_REV                    0x2200

#define DP_DP13_MAX_LINK_RATE               0x2201

# define DP_VSC_EXT_CEA_SDP_SUPPORTED			(1 << 6)  /* DP 1.4 */

# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED		(1 << 7)  /* DP 1.4 */

/* Protocol Converter Extension */

/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */

#define DP_CEC_TUNNELING_CAPABILITY            0x3000

# define DP_CEC_TUNNELING_CAPABLE               (1 << 0)

#define DP_CEC_TX_MESSAGE_BUFFER               0x3020

#define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10

/* HDCP 1.3 and HDCP 2.2 */

#define DP_AUX_HDCP_BKSV		0x68000

#define DP_AUX_HDCP_RI_PRIME		0x68005

#define DP_AUX_HDCP_AKSV		0x68007

#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET	0x69494

#define DP_HDCP_2_2_REG_DBG_OFFSET		0x69518

/* Link Training (LT)-tunable PHY Repeaters */

/* LTTPR: Link Training (LT)-tunable PHY Repeaters */

#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */

#define DP_MAX_LINK_RATE_PHY_REPEATER			    0xf0001 /* 1.4a */

#define DP_PHY_REPEATER_CNT				    0xf0002 /* 1.3 */